Skip to main content
SpringerLink
Log in

Analog-Digital Interfaces—Review and Current Trends

  • Chapter
  • First Online:
CHIPS 2020 VOL. 2

Part of the book series: The Frontiers Collection ((FRONTCOLL))

Abstract

By updating the figure-of-merit plots presented in CHIPS 2020 using new survey data collected over the years 2011–2015, this chapter discusses asymptotes and extracts recent improvement rates in the area of low-power, high-performance A/D conversion. Moreover, five years after the writing of CHIPS 2020, the developments in current architectures will be re-iterated, and the emerging concept of analog-to-information conversion will be discussed.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 59.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    We define the conversion bandwidth as the highest input frequency for which the plotted SNDR was measured. This frequency is typically fs/2 with exceptions noted in the fin_hf column of [2].

References

  1. Keller, M., Murmann, B., Manoli, Y.: Analog-digital interfaces. In: Hoefflinger, B. (ed.) CHIPS 2020—A Guide to the Future of Nanoelectronics, pp. 95–130. Springer, Berlin (2012)

    Google Scholar 

  2. Murmann, B.: ADC performance survey 1997–2015. Available http://web.stanford.edu/~murmann/adcsurvey.html

  3. Walden, R.H.: Analog-to-digital converter survey and analysis. IEEE J. Sel. Areas Commun. 17(4), 539–550 (1999)

    Article  Google Scholar 

  4. Schreier, R., Temes, G.C.: Understanding Delta-Sigma Data Converters. Wiley, New York (2005)

    Google Scholar 

  5. Ali, A.M.A., et al.: A 16-bit 250-MS/s IF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuits 45(12), 2602–2612 (2010)

    Article  Google Scholar 

  6. Ali, A.M.A.: A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs Jitter. IEEE J. Solid-State Circuits 41(8), 1846–1855 (2006)

    Article  Google Scholar 

  7. Ali, A.M.A., et al.: A 14 Bit 1 GS/s RF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuits 49(12), 2857–2867 (2014)

    Article  Google Scholar 

  8. Greshishchev, Y.M., et al.: A 40GS/s 6b ADC in 65 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest of Technical Papers, pp. 390–391 (2010)

    Google Scholar 

  9. Elliott, M., Murmann, B.: High-performance pipelined ADCs for wireless infrastructure systems. In: Manganaro, G., Leenaerts, D.M.W. (eds.) Advances in Analog and RF IC Design for Wireless Communication Systems. Elsevier, Amsterdam (2013)

    Google Scholar 

  10. Murmann, B.: Energy limits in A/D converters. In: 2013 IEEE Faible Tension Faible Consommation, pp. 1–4 (2013)

    Google Scholar 

  11. Bannon, A., et al.: An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range. In: IEEE Symposium of VLSI Circuits—Digest Technical Papers, pp. 1–2 (2014)

    Google Scholar 

  12. Lim, Y., Flynn, M.P.: A 1 mW 71.5 dB SNDR 50 MS/s 13 b fully differential ring amplifier based SAR-assisted pipeline ADC in 65 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 458–459 (2015)

    Google Scholar 

  13. Verbruggen, B., et al.: A 70 dB SNDR 200MS/s 2.3 mW dynamic pipelined SAR ADC in 28 nm digital CMOS. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 1–2 (2014)

    Google Scholar 

  14. Kull, L. et al.: A 90 GS/s 8 b 667 mW 64x interleaved SAR ADC in 32 nm Digital SOI CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 378–379 (2014)

    Google Scholar 

  15. Vittoz, E.A.: Future of analog in the VLSI environment. In: Proceedings of IEEE International Symposium on Circuits System, pp. 1372–1375 (1990)

    Google Scholar 

  16. Hosticka, B.J.: Performance comparison of analog and digital circuits. Proc. IEEE 73(1), 25–29 (1985)

    Article  Google Scholar 

  17. Bolatkale, M., et al.: A 4 GHz CT ΔΣ ADC with 70 dB DR and −74 dBFS THD in 125 MHz BW. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 470–472 (2011)

    Google Scholar 

  18. Tai, H.-Y., et al.: A 0.85 fJ/conversion-step 10 b 200 kS/s subranging SAR ADC in 40 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 196–197 (2014)

    Google Scholar 

  19. Doris, K., et al.: A 480 mW 2.6 GS/s 10 b 65 nm CMOS time-interleaved ADC with 48.5 dB SNDR up to Nyquist. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 180–182 (2011)

    Google Scholar 

  20. van der Goes, F., et al.: 11.4 A 1.5 mW 68 dB SNDR 80 MS/s 2× interleaved SAR-assisted pipelined ADC in 28 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 200–201 (2014)

    Google Scholar 

  21. Lee, C.C., Flynn, M.P.: A SAR-assisted two-stage pipeline ADC. IEEE J. Solid-State Circuits 46(4), 859–869 (2011)

    Article  Google Scholar 

  22. Kapusta, R., Decker, S., Ibaragi, E.: A 14 b 80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 472–473 (2013)

    Google Scholar 

  23. Harpe, P., Cantatore, E., van Roermund, A.: A 10 b/12 b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1 b ENOB at 2.2 fJ/conversion-step. IEEE J. Solid-State Circuits 48(12), 3011–3018 (2013)

    Article  Google Scholar 

  24. Kraemer, M., et al.: A 14 b 35 MS/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in 40 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 284–285 (2015)

    Google Scholar 

  25. Verbruggen, B., Iriguchi, M., Craninckx, J.: A 1.7 mW 11 b 250 MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 466–468 (2012)

    Google Scholar 

  26. Hershberg, B., et al.: Ring amplifiers for switched-capacitor circuits. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 460–462 (2012)

    Google Scholar 

  27. Lim, Y., Flynn, M.P.: 11.5 A 100 MS/s 10.5 b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 202–203 (2014)

    Google Scholar 

  28. Chang, D.-Y., et al.: 11.6 A 21 mW 15 b 48 MS/s zero-crossing pipeline ADC in 0.13 μm CMOS with 74 dB SNDR. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 204–205 (2014)

    Google Scholar 

  29. Dolev, N., Kramer, M., Murmann, B.: A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end. In: IEEE Symposium VLSI Circuits—Digest Technical Papers, pp. 98–99 (2013)

    Google Scholar 

  30. Chai, Y., Wu, J.-T.: A 5.37 mW 10 b 200 MS/s dual-path pipelined ADC. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 462–464 (2012)

    Google Scholar 

  31. Verma, S., et al.: A 10.3 GS/s 6 b flash ADC for 10 G Ethernet applications. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 462–463 (2013)

    Google Scholar 

  32. Chen, V.H.-C., Pileggi, L.: 22.2 A 69.5 mW 20 GS/s 6 b time-interleaved ADC with embedded time-to-digital calibration in 32 nm CMOS SOI. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 380–381 (2014)

    Google Scholar 

  33. Shu, Y.-S.: A 6 b 3 GS/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 26–27 (2012)

    Google Scholar 

  34. Narasimha, R., et al.: BER-optimal analog-to-digital converters for communication links. IEEE Trans. Signal Process. 60(7), 3683–3691 (2012)

    Article  MathSciNet  ADS  Google Scholar 

  35. Setterberg, B., et al.: A 14 b 2.5 GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 466–467 (2013)

    Google Scholar 

  36. Wu, J., et al.: A 5.4 GS/s 12 b 500 mW pipeline ADC in 28 nm CMOS. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 92–93 (2013)

    Google Scholar 

  37. Sun, N., Lee, H.-S., Ham, D.: A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. In: Proceedings of European Solid-State Circuits Conference, pp. 269–272 (2012)

    Google Scholar 

  38. Le Dortz, N., et al.: 22.5 A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70 dBFS. In: IEEE International Solid-State Circuits Conference—Digital Technical Papers, pp. 386–388 (2014)

    Google Scholar 

  39. Rao, S., et al.: A 4.1 mW, 12-bit ENOB, 5 MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90 nm CMOS. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 68–69 (2013)

    Google Scholar 

  40. Taylor, G., Galton, I.: A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160 dB. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 166–167 (2012)

    Google Scholar 

  41. de la Rosa, J.M.: CMOS SDMs Survey. Available http://www.imse-cnm.csic.es/~jrosa/CMOS-SDMs-Survey-IMSE-JMdelaRosa.xlsx

  42. Yoon, D.-Y., Ho, S., Lee, H.-S.: An 85 dB DR 74.6 dB SNDR 50 MHz BW CT MASH delta-sigma modulator in 28 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 272–273 (2015)

    Google Scholar 

  43. Zhang, J., et al.: A 0.6 V 82 dB 28.6 µW continuous-time audio delta-sigma modulator. IEEE J. Solid-State Circuits 46(10), 2326–2335 (2011)

    Article  Google Scholar 

  44. Michel, F., Steyaert, M.S.: A 250 mV 7.5 μW 61 dB SNDR SC delta-sigma modulator using near-threshold-voltage-biased inverter amplifiers in 130 nm CMOS. IEEE J. Solid-State Circuits 47(3), 709–721 (2012)

    Article  Google Scholar 

  45. Yang, Z., Yao, L., Lian, Y.: A 0.5 V 35 µW 85 dB DR double-sampled delta-sigma modulator for audio applications. IEEE J. Solid-State Circuits 47(3), 722–735 (2012)

    Article  Google Scholar 

  46. Philips, K., et al.: A continuous-time sigma-delta ADC with increased immunity to interferers. IEEE J. Solid-State Circuits 39(12), 2170–2178 (2004)

    Article  Google Scholar 

  47. Rajan, R.S., Pavan, S.: Design techniques for continuous-time delta-sigma modulators with embedded active filtering. IEEE J. Solid-State Circuits 49(10), 2187–2198 (2014)

    Article  Google Scholar 

  48. Andersson, M., et al.: A filtering ΔΣ ADC for LTE and beyond. IEEE J. Solid-State Circuits 49(7), 1535–1547 (2014)

    Article  Google Scholar 

  49. Chae, Y., Han, G.: A low power sigma-delta modulator using class-C inverter. In: IEEE Symposium VLSI Circuits—Digest Technical Papers, pp. 240–241 (2007)

    Google Scholar 

  50. Chae, Y., Lee, I., Han, G.: A 0.7 V 36 μW 85 dB-DR audio delta-sigma modulator using Class-C inverter. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 490–491 (2008)

    Google Scholar 

  51. van Veldhoven, R.H.M., Rutten, R., Breems, L.J.: An inverter-based hybrid delta-sigma modulator. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 492–493 (2008)

    Google Scholar 

  52. Chae, Y., Han, G.: Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator. IEEE J. Solid-State Circuits 44(2), 458–472 (2009)

    Article  Google Scholar 

  53. Perez, A.P., Bonizzoni, E., Maloberti, F.: A 84 dB SNDR 100 kHz bandwidth low-power single op-amp third-order delta-sigma modulator consuming 140 μW. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 478–480 (2011)

    Google Scholar 

  54. Chae, H., et al.: A 12 mW low-power continuous-time bandpass delta-sigma modulator with 58 dB SNDR and 24 MHz bandwidth at 200 MHz IF. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 148–150 (2012)

    Google Scholar 

  55. Matsukawa, K., et al.: A 10 MHz BW 50 fJ/conv. continuous time delta-sigma modulator with high-order single opamp integrator using optimization-based design method. In: IEEE Symposium on VLSI Circuits—Digital Technical Papers, pp. 160–161 (2012)

    Google Scholar 

  56. Christen, T.: A 15bit 140 µW scalable-bandwidth inverter-based Delta-Sigma modulator for a MEMS microphone with digital output. IEEE J. Solid-State Circuits 48(7), 1605–1614 (2013)

    Article  Google Scholar 

  57. Zeller, S., et al.: A 0.039 mm2 inverter-based 1.82mW 68.6 dB SNDR 10 MHz BW CT Sigma-Delta ADC in 65 nm CMOS using power- and area-efficient design techniques. IEEE J. Solid-State Circuits 49(7), 1548–1560 (2014)

    Article  Google Scholar 

  58. Weng, C.-H., et al.: An 8.5 MHz 67.2 dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90 nm CMOS. In: IEEE Symposium on VLSI Circuits—Digital Technical Papers, pp. 1–2 (2014)

    Google Scholar 

  59. Straayer, M.Z., Perrott, M.H.: A 12-Bit, 10-MHz bandwidth, continuous-time sigma-delta ADC with a 5-Bit, 950-MS/s VCO-based quantizer. IEEE J. Solid-State Circuits 43(3), 805–814 (2008)

    Article  Google Scholar 

  60. Park, M., Perrott, M.H.: A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time delta-sigma ADC with VCO-based integrator and quantizer implemented in 0.13 µm CMOS. IEEE J. Solid-State Circuits 44(12), 3344–3358 (2009)

    Article  Google Scholar 

  61. Reddy, K., et al.: A 16 mW 78 dB SNDR 10 MHz BW CT delta-sigma ADC using residue-cancelling VCO-based quantizer. IEEE J. Solid-State Circuits 47(12), 2916–2927 (2012)

    Article  Google Scholar 

  62. Asl, S.Z., et al.: A 77 dB SNDR, 4 MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. In: Proceedings of IEEE Custom Integrated Circuits Conference, pp. 1–4 (2011)

    Google Scholar 

  63. Daniels, J., Dehaene, W., Steyaert, M.: A 0.02 mm2 65 nm CMOS 30 MHz BW all-digital differential VCO-based ADC with 64 dB SNDR. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 155–156 (2010)

    Google Scholar 

  64. Taylor, G., Galton, I.: A mostly-digital variable-rate continuous-time delta-sigma modulator ADC. IEEE J. Solid-State Circuits 45(12), 2634–2646 (2010)

    Article  Google Scholar 

  65. Rao, S., et al.: A 71 dB SFDR open loop VCO-based ADC using 2-level PWM modulation. In: IEEE Symposium on VLSI Circuits—Digest Technical Papers, pp. 270–271 (2011)

    Google Scholar 

  66. Taylor, G., Galton, I.: A reconfigurable mostly-digital delta-sigma ADC with a worst-case FOM of 160 dB. IEEE J. Solid-State Circuits 48(4), 983–995 (2013)

    Article  Google Scholar 

  67. Rao, S., et al.: A deterministic digital background calibration technique for VCO-based ADCs. IEEE J. Solid-State Circuits 49(4), 950–960 (2014)

    Article  Google Scholar 

  68. Prefasi, E., et al.: A 0.1 mm2 wide bandwidth continuous-time Sigma-Delta ADC based on a time encoding quantizer in 0.13 µm CMOS. IEEE J. Solid-State Circuits 44(10), 2745–2754 (2009)

    Article  Google Scholar 

  69. De Vuyst, B., Rombouts, P.: A 5 MHz 11Bit self-oscillating sigma-delta modulator with a delay-based phase shifter in 0.025mm2. IEEE J. Solid-State Circuits 46(8), 1919–1927 (2011)

    Article  Google Scholar 

  70. Prefasi, E., Paton, S., Hernandez, L.: A 7 mW 20 MHz BW time-encoding oversampling converter implemented in a 0.08 mm2 65 nm CMOS circuit. IEEE J. Solid-State Circuits 46(7), 1562–1574 (2011)

    Article  Google Scholar 

  71. Dhanasekaran, V., et al.: A continuous-time multi-bit delta-sigma ADC using time domain quantizer and feedback element. IEEE J. Solid-State Circuits 46(3), 639–650 (2011)

    Article  Google Scholar 

  72. Dhanasekaran, V., et al.: A 20 MHz BW 68 dB DR CT delta-sigma ADC based on a multi-bit time-domain quantizer and feedback element. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 174–175, 175a (2009)

    Google Scholar 

  73. Oliaei, O.: Sigma-delta modulator with spectrally shaped feedback. IEEE Trans. Circuits Syst. II, Analog Dig. Signal Process. 50(9), 518–530 (2003)

    Article  Google Scholar 

  74. Putter, B.: Sigma-delta ADC with finite impulse response feedback DAC. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 76–76 (2004)

    Google Scholar 

  75. Shettigar, P., Pavan, S.: A 15 mW 3.6 GS/s CT delta-sigma ADC with 36 MHz bandwidth and 83 dB DR in 90 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 156–158 (2012)

    Google Scholar 

  76. Srinivasan, V.: A 20 mW 61 dB SNDR (60 MHz BW) 1 b 3rd-order continuous-time delta-sigma modulator clocked at 6 GHz in 45 nm CMOS. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 158–160 (2012)

    Google Scholar 

  77. Shettigar, P., Pavan, S.: Design techniques for wideband single-bit continuous-time Delta-Sigma modulators with FIR feedback DACs. IEEE J. Solid-State Circuits 47(12), 2865–2879 (2012)

    Article  Google Scholar 

  78. Healy, D., Brady, D.J.: Compression at the physical interface. IEEE Signal Process. Mag. 25(2), 67–71 (2008)

    Article  ADS  Google Scholar 

  79. Candes, E.J., Romberg, J., Tao, T.: Robust uncertainty principles: exact signal reconstruction from highly incomplete frequency information. IEEE Trans. Inf. Theory 52(2), 489–509 (2006)

    Article  MATH  MathSciNet  Google Scholar 

  80. Candes, E.J., Wakin, M.B.: An introduction to compressive sampling. IEEE Signal Process. Mag. 25(2), 21–30 (2008)

    Article  ADS  Google Scholar 

  81. Gangopadhyay, D., et al.: Compressed sensing analog front-end for bio-sensor applications. IEEE J. Solid-State Circuits 49(2), 426–438 (2014)

    Article  Google Scholar 

  82. Oike, Y., El Gamal, A.: CMOS image sensor with per-column ΣΔ ADC and programmable compressed sensing. IEEE J. Solid-State Circuits 48(1), 318–328 (2013)

    Article  Google Scholar 

  83. Yoo, J., et al.: A 100 MHz–2 GHz 12.5x sub-Nyquist rate receiver in 90 nm CMOS. In: Proceedings of RF IC Symposium, pp. 31–34 (2012)

    Google Scholar 

  84. Abari, O., et al.: Performance trade-offs and design limitations of analog-to-information converter front-ends. In: Proceedings of International Conference Acoustics, Speech, Signal Processing, pp. 5309–5312 (2012)

    Google Scholar 

  85. Mishali, M., Eldar, Y.: Sub-Nyquist sampling. IEEE Signal Process. Mag. 28(6), 98–124 (2011)

    Article  ADS  Google Scholar 

  86. Vetterli, M., Marziliano, P., Blu, T.: Sampling signals with finite rate of innovation. IEEE Trans. Signal Process. 50(6), 1417–1428 (2002)

    Article  MathSciNet  ADS  Google Scholar 

  87. Tur, R., Eldar, Y.C., Friedman, Z.: Innovation rate sampling of pulse streams with application to ultrasound imaging. IEEE Trans. Signal Process. 59(4), 1827–1842 (2011)

    Article  MathSciNet  ADS  Google Scholar 

  88. Muramatsu, Y., et al.: A signal-processing CMOS image sensor using a simple analog operation. IEEE J. Solid-State Circuits 38(1), 101–106 (2003)

    Article  MathSciNet  Google Scholar 

  89. Choi, J., et al.: A 3.4-μW object-adaptive CMOS image sensor with embedded feature extraction algorithm for motion-triggered object-of-interest imaging. IEEE J. Solid-State Circuits 49(1), 289–300 (2014)

    Article  Google Scholar 

  90. Badami, K., et al.: Context-aware hierarchical information-sensing in a 6 μW 90 nm CMOS voice activity detector. In: IEEE International Solid-State Circuits Conference—Digest Technical Papers, pp. 430–431 (2015)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Microsystems Engineering—IMTEK, University of Freiburg, Georges-Koehler-Allee 102, 79110, Freiburg, Germany

    Matthias Keller & Yiannos Manoli

  2. Stanford University, 420 Via Palou, Allen 208, Stanford, CA, 94305-4070, USA

    Boris Murmann

Authors
  1. Matthias Keller
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Boris Murmann
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yiannos Manoli
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Matthias Keller .

Editor information

Editors and Affiliations

  1. Institute for Microelectronics, Sindelfingen, Germany

    Bernd Höfflinger

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Keller, M., Murmann, B., Manoli, Y. (2016). Analog-Digital Interfaces—Review and Current Trends. In: Höfflinger, B. (eds) CHIPS 2020 VOL. 2. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-319-22093-2_4

Download citation

Publish with us

Policies and ethics

Search

Navigation