Abstract
The number of integrated transistors has increased so rapidly that it has become evident that a further increase of the performance is limited by the power dissipation. The future IT and electronics, therefore, require more efficient power-reduction solutions. In the human brain and nerve system, analog signals from sensing orgasms are processed by a network composed of neurons and synapses. This process is slow but very power-efficient because it is done by below-100 mV signal levels.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
JEITA Green IT Promotion Council.: Report 2008–2012, Feb 2013
Koomey, J.G., Berard, S., Sanchez, M., Wong, H.: Assessing trends in the electrical efficiency of computation over time. In: IEEE Annals of the History of Computing, 17 Aug 2009
Wanlass, F.M., Sah, C.T.: Nanowatt logic using field-effect metal-oxide-semiconductor triodes. In: International Solid-State Circuits Conference Digest Technical Papers, pp. 58–59, Feb 1963
Masuhara, T., Minato, O., Sasaki, Y., Sakai, Y., Kubo, M., Yasui, T.: A high-speed low-power hi-CMOS 4 K static RAM. In: International Solid-State Circuits Conference Digest Technical Papers, pp. 110–111, Feb 1978
Chen, T.C.: Where CMOS is going. IEEE SSCS Newslett. 20(3), 5–8 (2006)
Tanaka, H., Kido, M., Yahashi, K., Oomura, M., Katsumata, R., Kito, M., Fukuzumi, Y., Sato, M., Nagata, Y., Matsuoka, Y., Iwata, Y., Aochi, H., Nitayama, A.: Bit cost scalable technology with punch and plug process for ultra high density flash memory. In: 2007 VLSI Technical Symposium, Digest Technical Papers, pp. 14–15, June 2007
Tsuchiya, R., Horiuchi, M., Kimura, S., Yamaoka, M., Kawahara, T., Maegawa, S., Ipposhi, T., Ohji, Y., Matsuoka, H.: Silicon on thin BOX: a new paradigm of the CMOSFET for low-power high-performance application featuring wide-range back-bias control. In: IEDM Technical Digest, pp. 631–634, Dec 2004
Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Kha, P.C., Makiyama, H., Yamamoto, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Hung, L.D., Yomogita, T., Kudo, M., Kitamori, K., Kondo, S., Manza, Y.: A perpetuum mobile 32 bit CPU with 13.4 pJ/cycle, 0.14 μA sleep current using reverse body bias assisted 65 nm SOTB CMOS technology. In: Proceedings 2014 IEEE Cool Chips XVII, Apr 2014
NEDO Final Evaluation Report, on the Research project.: fundamentals of next generation semiconductor material and process, MIRAI Project-3rd Phase (Japanese). Oct 2011
Hiramoto, T., Mizutani, T., Kumar, A., Nishida, A., Tsunomura, T., Inaba, S., Takeuchi, K., Kamohara, S., Mogami, T.: Suppression of DIBL and current onset voltage variability in intrinsic channel FD SOI MOSFETs. In: 2010 International SOI Conference
Yamamoto, Y., Makiyama, H., Tsunomura, T., Iwamatsu, T., Oda, H., Sugii, N., Yamaguchi, Y., Mizutani, T., Hiramoto, T.: Poly/high-k/SiON gate and novel profile engineering for low power silicon on thin BOX (SOTB) CMOS operation. In: 2012 VLSI Technical Symposium, Digest Technical Papers, pp. 109–110, June 2012
Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T., Hiramoto, T.: Ultralow-voltage operation down to 0.37 V of silicon-on-thin-box (SOTB) 2 Mbit SRAM utilizing adaptive body bias. In: 2013 VLSI Technical Symposium, Digest Technical Papers, pp. T212–T213, June 2013
Soo, H.L., Amano, Y.: Evaluation of low power reconfigurable accelerator chip using SOTB transistor (Japanese). In: Technical Digest IEICE, 113, No. 325, RECONF2013-52, Nov 2013
Horowitz, M.: Computing’s energy problem: (and what we can do about it). In: International Solid-State Circuits Conference Digest Technical Papers, pp. 10–14, Feb 2014
Iba, Y., Yoshida, C., Hatada, A., Nakabayashi, M., Takahashi, A., Yamazaki, Y., Noshiro, H., Tsunoda, K., Takenaga, T., Aoki, M., Sugii, T.: Top-pinned perpendicular structure with a counter bias magnetic field layer for suppressing a stray-field in highly scalable STT-MRAM. In: Digest Technical Papers, VLSI Technical Symposium, pp. 11–13, June 2013
Yoshida, C., Ochiai, T., Iba, Y., Yamazaki, Y., Tsunoda, K., Takahashi, A., Sugii, T.: Demonstration of non-volatile working memory through interface engineering in STT-MRAM. In: Digest Technical Papers, VLSI Technical Symposium, pp. 12–14, June 2012
Iba, Y., Takahashi, A., Hatada, A., Nakabayashi, M., Yoshida, C., Yamazaki, Y., Tsunoda, K., Sugii, T.: A highly scalable STT-MRAM fabricated by a novel technique for shrinking a magnetic tunnel junction with reducing processing damage. In: 2014 VLSI Technical Symposium, pp. 58–59, June 2014
Miyamura, M., Tada, M., Sakamoto, T., Banno, N., Okamoto, K., Iguchi, N., Hada, H.: First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch. In: IEDM Technical Digest, pp. 10.6.1–10.6.4, Dec 2012
Tada, M., Sakamoto, T., Banno, N., Okamoto, K., Miyamura, M., Iguchi, N., Nohisa, T., Hada, H.: Highly reliable, complementary atom switch (CAS) with low programming voltage embedded in Cu BEOL for nonvolatile programmable logic. In: IEDM Technical Digest, pp. 30.2.1–30.2.4, Dec 2011
Banno, N., Tada, M., Sakamoto, T., Miyamura, M., Okamoto, K., Iguchi, N., Nohisa, T., Hada, H.: A fast and low-voltage Cu complementary-atom-switch 1 Mb array with high-temperature retention. In: 2014 VLSI Technical Symposium, pp. 202–203, June 2014
Tada, M., Sakamoto, T., Banno, N., Okamoto, K., Miyamura, M., Iguchi, N., Hada, H.: Improved reliability and switching performance of atom switch by using ternary Cu-alloy and RuTa electrodes. In: IEDM Technical Digest, pp. 29.8.1–29.8.4, Dec 2012
Hada, H.: In: Technical Digest, 3rd LEAP FORUM on Ultra Low Voltage Device Project for Low Carbon Society, Tokyo, Japan, Jan 23, 2014
Sakamoto, T., Tada, M., Tsuji, Y., Makiyama, H., Hasegawa, T., Yamamoto, Y., Okanishi, S., Banno, N., Miyamura, M., Okamoto, K., Iguchi, N., Ogasawara, Y., Oda, H., Kamohara, S., Yamagata, Y., Sugii, N., Hada, H.: Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor. Appl. Phys. Express 8, 045201 (2015). doi:10.7567/APEX.8.045201
Sakamoto, T., Tsuji, Y., Tada, M., Makiyama, H., Hasegawa, T., Yamamoto, Y., Okanishi, S., Maekawa, K., Banno, N., Miyamura, M., Okamoto, K.. Iguchi, N., Ogasahara, Y., Oda, H., Kamohara, S., Yamagata, Y., Sugii, N., Hada, H.: 0.39-V 18.26-μW/MHz SOTB CMOS microcontroller with embedded atom switch ROM. In: Proceedings of 2015 IEEE Cool Chips XVIII, Apr 2015
Simpson, R.E., Fons, P., Kolobov, A.V., Fukaya, T., Krbal, M., Yagi, Y., Tominaga, J.: Interfacial phase change memory. Nat. Nanotechnol. 6, 501–505 (2011). doi:10.1038/nnano.2011.96
Tai, M., Ohyanagi, T., Kinoshita, M., Morikawa, T., Akita, K., Kato, S., Shirakawa, H., Araidai, M., Shiraishi K., Takaura, N.: 1T-1R pillar-type topological-switching random access memory (TRAM) and data retention of GeTe/Sb2Te3 super-lattice films. In: Digest Technical Papers, VLSI Technical Symposium, pp. 9–12, June 2014
Ohyanagi, T., Takaura, N., Tai, M., Kitamura, M., Kinoshita, M., Akita, K., Morikawa, T., Kato, S., Araidai, M., Kamiya, K., Yamamoto, T., Shiraishi, K.: Charge-injection phase change memory with high-quality GeTe/Sb2Te3 superlattice featuring 70-μA RESET, 10-ns SET and 100 M endurance cycles operations. In: IEDM Technical Digest, pp. 30.5.1–30.5.4, Dec 2013
Takaura, N., Ohyanagi, T., Tai, M., Kinoshita, M., Akita, K., Morikawa, T., Shirakawa, H., Araidai, M., Shiraishi, K., Saito, Y., Tominaga, J.: 55-μA GexTe1-x/Sb2Te3 superlattice topological-switching random-access memory (TRAM) and study of atomic arrangement in GeTe/Sb2Te3 structures. In: IEDM Technical Digest, Dec 2014
Naeemi, A., Meindl, J.D.: Conductance modeling for graphene nanoribbon (GNR) interconnects. IEEE Electron Device Lett. 28, 428–431 (2007)
Sakai, T.: Technical Digest, 3rd LEAP FORUM on Ultra Low Voltage Device Project for Low Carbon Society, Tokyo, Japan, 23 Jan 2014
Sakai, T.: In: Technical Digest, 4th LEAP FORUM on Ultra Low Voltage Device Project for Low Carbon Society, Tokyo, Japan, 6 Mar 2015
Fukushima, T., Yamada, Y., Kikuchi, H., Koyanagi, M.: New 3D-integration technology using self-assembly technique. In: IEDM Technical Digest, pp. 359–363, Dec 2005
Hanamura, S., Aoki, M., Masuhara, T., Minato, O., Sasaki, Y., Sakai, Y., Hayashida, T.: Operation of bulk CMOS devices at very low temperatures. IEEE J. Solid-State Circuits, 21(3), 484–490 1986
Masuhara, T., Nagata, M., Hashimoto, N., A high performance N-channel MOSLSI using depletion-type load elements. In: International Solid-State Circuits Conference Digest Technical Papers, pp. 12–13, Feb 1971
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Masuhara, T. (2016). The Future of Low-Power Electronics. In: Höfflinger, B. (eds) CHIPS 2020 VOL. 2. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-319-22093-2_2
Download citation
DOI: https://doi.org/10.1007/978-3-319-22093-2_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-22092-5
Online ISBN: 978-3-319-22093-2
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)