Abstract
Computing with nano-chip technologies spans highly different applications. The corresponding processor-chips span a range of 1000:1 in performance and in their energy-efficiency. From 2010 to 2014, their performance per product-unit almost doubled every year, while their energy efficiency doubled only every three years, so that their total power consumption quadrupled in three years. With the evidence of this energy crisis , the projections for 2015–2020 have been corrected somewhat to a global performance improvement of 20-times in 5 years, while the energy efficiency shall improve an optimistic 7-times in 5 years, which would raise the total required wall-plug power another 3-times, an unlikely scenario, accompanied by a “Green” movement. This “green ” strategy lowers the energy per operation by reducing the operating voltage. However, this reduces the operations per second so much that, wherever the completion of operations in a given time is an issue, more computing units would have to be run in parallel, with a worse balance in required hardware and energy. Therefore, GREEN is not enough. A new throughput figure-of-merit sheds new light on the task of simultaneously improving performance and energy-efficiency, demanding disruptive innovations.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Hoefflinger, B.: Towards terabit memory, Chap. 11. In: Hoefflinger, B. (ed.) CHIPS 2020—A Guide to the Future of Nanoelectronics. Springer, Berlin (2012). doi:10.1007/978-3-64223096-7_11
Fluhr, E.J. et al.: POWER8TM: A 12-core server-class processorin 22 nm SOI with 7.6 Tb/s off-chip bandwidth. In: IEEE 2014 International Solid-State Circuits Conference Digest of Technical Papers, pp. 96–97, Feb 2014
Kim, G. et al.: A 1.2 TOPS and 1.52 mW/MHz augmented-reality multi-core processor with neural-network NOC for HMD applications, ibid. pp. 182–184
Park, S. et al.: A 1.93 TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications, 2015 ISSCC Digest of Technical Papers, paper 4.6, 2015
DARPA, Ubiquitous High-Performance Computing (UHPC), DARPA_BAA-10-37_final_3-2-10_post_(2).pdf. (2010)
Hoefflinger, B.: The energy crisis, Chap. 20. In: Hoefflinger, B. (ed) CHIPS 2020—A Guide to the Future of Nanoelectronics, Chap. 11. Springer, Berlin (2012). doi:10.1007/978-3-64223096-7_20
Raghavan, B., Ma, J.: The Energy and Emergy of the Internet, ICSI and UC Berkeley 2011. Copyright 2011 ACM 978-1-4503-1059-8/11/11. http://goo.gl/y4juZ
www:eia.gov/installed-electric-power
Borkar, S.: Exascale Computing—Fact or Fiction? SSCS Webinar, September 2014
Horowitz, M.: Computing’s Energy Problem (and what we can do about it), IEEE ISSCC 2014, Dig. Tech. Papers pp. 10–14
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Hoefflinger, B. (2016). High-Performance Computing (HPC ). In: Höfflinger, B. (eds) CHIPS 2020 VOL. 2. The Frontiers Collection. Springer, Cham. https://doi.org/10.1007/978-3-319-22093-2_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-22093-2_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-22092-5
Online ISBN: 978-3-319-22093-2
eBook Packages: Physics and AstronomyPhysics and Astronomy (R0)