Abstract
With the move to multicore computing, the demand for memory bandwidth grows with the number of cores. It is predicted that multicore computers will need 1 TBps of memory bandwidth. However, memory device scaling is facing increasing challenges due to the limited number of read and write cycles in flash memories and capacitor-scaling limitations for DRAM cells. Therefore, memory bottleneck is one of the main challenges in modern VLSI design. Microprocessors communicate with memory cores through memory controllers (Fig. 3.1). A detailed figure is shown in Fig. 3.2 [1–6].
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Mohamed, K.S. (2016). Analyzing the Trade-off Between Different Memory Cores and Controllers. In: IP Cores Design from Specifications to Production. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-22035-2_3
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DOI: https://doi.org/10.1007/978-3-319-22035-2_3
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