Abstract
As stated earlier in the previous chapter, plug and play IP in SoC design is the recent trend in VLSI design (Fig. 2.1). IP cores life cycle process from specification to production includes four major steps: (1) IP modeling, (2) IP verification, (3) IP optimization, (4) IP protection. These steps are elaborated in Fig. 2.2. In the next sections, we will discuss each step in detail.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rafla NI, Davis, Brett LaVoy (2006) A study of finite state machine coding styles for implementation in FPGAs. 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan
Roudier T, Moussa I, di Crescenzo P (2003) IP modelling and reuse for system level design. Published for DATE
Simpson P, Jagtiani A (2007) How to achieve faster compile times in high-density FPGA. EE Times
Ricardo R, Marcelo L, Jochen J (2010) Design of systems on chip: design and test. Springer, Dordrecht
Clive M (ed) (2007) FPGAs: world class design. Newness, Burlington
Hauck S, DeHon A (2008) Reconfigurable computing: the theory and practice of FPGA-based computation. Morgan Kaufmann, Burlington
Maxfield CM (2004) The design warrior’s guide to FPGAs. Newnes, Burlington
Betz V, Rose J, Marquardt A (1999) Architecture and CAD for deep-submicron FPGAs. Kluwer, Boston
Sutherland S, Davidmann S, Flake P (2003) Systemverilog for design: a guide to using systemverilog for hardware design and modeling. Kluwer, Norwell
Black D, Donovan J, Bunton B, Keist A (2010) SystemC: from the ground up, 2nd edn. Springer, New York. ISBN 978-0-387-69957-8
Goel P, Adhikari S (2014) Introduction to next generation verification language—Vlang. DVCON Conference and Exhibition, Munich
Schwartz RL, Phoenix T (2008) Learning PERL. O’Reilly Media, Sebastopol
Ucoluk G, Kalkan S (2007) Introduction to programming concepts with case studies in python. Springer, London
IEEE 1685-2009 IPXACT. Accessed 18 Feb 2010
Kulkarni R (2013) Automated RTL generator. M.Sc. Thesis, San Jose State University
Axelson J (1997) The microcontroller idea book. Lakeview Research, Madison
Sherwani NA (1999) Algorithms for VLSI physical design automation, 3rd edn. Kluwer, Boston
Sung Kyu L (2008) Practical problems in VLSI physical design automation. Springer, New York
Clein D (2000) CMOS IC layout concepts, methodologies, and tools. Butterworth–Heinemann, Newton
Coombs CF Jr (2001) Printed circuits handbook. McGraw-Hill, New York
Masahiro F, Indradeep G, Mukul P (2008) Verification techniques for system-level design. Morgan Kaufmann, San Francisco
Khan MA, Pittman RN, Forin A (2010) gNOSIS: a board-level debugging and verification tool. Proceedings of the IEEE Conference on ReConFigurable Computing and FPGAs (ReConFig), Microsoft Research, Redmond. pp 43–48
Pradhan DK, Harris IG (2009) Practical design verification. Cambridge University Press, Cambridge
Singh L, Drucker L, Khan N (2004) Advanced verification techniques: a SystemC based approach for successful. Kluwer, Boston
Scheffer L, Lavagno L, Martin G (2006) EDA for IC system design, verification, and testing. CRC, Boca Raton
Cassel M, Kastensmidt FL (2006) Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs. Proceedings of 12th IEEE International On-Line Testing Symposium (IOLTS 2006), IEEE, Washington, p 6
http://www.arm.com/files/pdf/New_Whitepaper_Layout_Solving_Next_Generation_IP_Configurability.pdf. Accessed 2015
Bhuvaneswari K, Srinivasa Rao V (2013) Dynamic partial reconfiguration in low-cost FPGAs. Int J Sci Eng Res 4(9):1410–1413
Drahonovsky T, Rozkovec M, Novak O (2013) Relocation of reconfigurable modules on Xilinx FPGA. Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Karlovy Vary, pp 175–180
Partial reconfiguration user guide, Ug702 (v12.3) ed., Xilinx Corporation, October 2012
Partial reconfiguration of Xilinx FPGAs using ISE design suite, Xilinx Corporation, July 2012
Dunkley R (2012) Supporting a wide variety of communication protocols using partial dynamic reconfiguration. Proc IEEE Autotestcon 2012:120–125
Marques N, Rabah H, Dabellani E, Weber S (2011) Partially reconfigurable entropy encoder for multi standards video adaptation. 2011 IEEE 15th International Symposium on Consumer Electronics (ISCE), June 2011, pp 492–496
Wang Lie, Wu Fengyan (2009) Dynamic partial reconfiguration in FPGA. Third International Symposium on Intelligent Information Technology Application, IEEE Computer Society, Nanchang, pp 445–448
Chakraborty RS, Bhunia S (2008) Hardware protection and authentication through netlist level obfuscation. Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, San Jose, 10–13 November 2008
Chakraborty RS, Bhunia S (2009) HARPOON: an obfuscation-based SoC design methodology for hardware protection. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1493–1502
Kainth M, Krishnan L, Narayana C, Virupaksha SG, Tessier R (2015) Hardware-assisted code obfuscation for FPGA soft microprocessors. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE, EDA Consortium, San Jose
Tehranipoor MM, Guin U, Forte D (2015) Counterfeit integrated circuits detection and avoidance. Springer, Cham
http://www.eetimes.com/electronics-news/4212418/Standard-issued-for-PCB-IP-protection
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Mohamed, K.S. (2016). IP Cores Design from Specifications to Production: Modeling, Verification, Optimization, and Protection. In: IP Cores Design from Specifications to Production. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-22035-2_2
Download citation
DOI: https://doi.org/10.1007/978-3-319-22035-2_2
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-22034-5
Online ISBN: 978-3-319-22035-2
eBook Packages: EngineeringEngineering (R0)