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PLL-Free, High Data Rate Capable Frequency Synthesizers

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Abstract

The PLL based frequency synthesizer has been the main impediment to achieve a low energy dissipation in the radios employed in Wireless Sensor Networks (WSN); in spite of duty cycling. This is due to the crystal oscillator reference in the frequency synthesizer which dissipates significant energy during its long wakeup phase. To address this issue and thereby obtain the full advantage proffered by duty cycling, an overview of FBAR based synthesizers which can wake up in just 5 μs is presented. In addition, these synthesizers can also support high data rates as compared to the PLL based radios, thereby offering the possibility to increase the rate of duty cycling and thus further lowering the average energy dissipation.

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Correspondence to Raghavasimhan Thiruarayanan .

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Thiruarayanan, R., Ruffieux, D., Enz, C. (2016). PLL-Free, High Data Rate Capable Frequency Synthesizers. In: Makinwa, K., Baschirotto, A., Harpe, P. (eds) Efficient Sensor Interfaces, Advanced Amplifiers and Low Power RF Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-21185-5_13

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  • DOI: https://doi.org/10.1007/978-3-319-21185-5_13

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-21184-8

  • Online ISBN: 978-3-319-21185-5

  • eBook Packages: EngineeringEngineering (R0)

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