Abstract
This paper will describe the design and implementation of a MIPS-based microprocessor using Bennett clocking to implement reversible logic. In Bennett clocking the clock signals form a “cascade” that moves information forward through logic gates in the compute phase, and then recovers energy during a decompute phase, forming a reversible logic circuit. New logic design and verification tools were developed, using structural Verilog and extensions to ModelSim to address the issues of adiabatic clocking, tools that are currently unavailable in commercial packages. The microprocessor is based on a simplified version of the MIPS architecture. After verification by our design tools it was then implemented using CMOS standard cells based on split-level charge recovery logic. The final design contains approximately 5700 transistors, and is currently being fabricated at MOSIS.
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References
Esmaeilzadeh, H., Blem, E., Amant, R., Sankaralingam, K., Burger, D.: ``Dark silicon and the end of multicore scaling’’. In: 38th Annual International Symposium on Computer Architecture. pp. 365–376. ACM (2011)
NRDC, “America’s Data Centers Consuming and Wasting Growing Amounts of Energy”. http://www.nrdc.org/energy/data-center-efficiency-assessment.asp
Landauer, R.: Irreversibility and Heat Generation in the Computing Process. IBM Journal of Research and Development 5, 183–191 (1961)
Costello, D.J., Forney, G.D.: Channel coding: The road to channel capacity. Proceedings of the IEEE 95, 1150–1177 (2007)
Cavin, R.K., Zhirnov, V.V., Hutchby, J.A., Bourianoff, G.I.: Energy barriers, demons, and minimum energy operation of electronic devices. Fluctuation and Noise Letters 5, C29–C38 (2005)
Zhirnov, V.V., Cavin, R.K., Hutchby, J.A., Bourianoff, G.I.: Limits to binary logic switch scaling - A Gedanken model. Proceedings of the IEEE 91, 1934–1939 (2003)
Orlov, A.O., Lent, C.S., Thorpe, C.C., Boechler, G.P., Snider, G.L.: Experimental Test of Landauer’s Principle at the Sub-kBT Level. Jpn. J. Appl. Phys 51, 06FE10-1–06FE10-5 (2012)
Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of Landauer’s principle linking information and thermodynamics. Nature 483, 187–189 (2012)
Vieri, C.J.: “Reversible Computer Engineering and Architecture” Massachusets Institute of Technology, Ph.D Thesis, (1999)
Lent, C.S., Liu, M., Lu, Y.H.: Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling. Nanotechnology 17, 4240–4251 (2006)
Valiev, K.A., Starosel’skii, V.I.: A Mondel and Properties of a Thermodynamically Reversible Logic Gate. Russian Microelectronics 29, 83–98 (2000)
Younis, S.: “Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic’’. Massachusets Institute of Technology, Ph.D. Thesis (1994)
Weste, N., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspectives. 4th ed. Addison-Wesley (2010)
MOSIS, “MOSIS, Wafer Electrical Test’’. https://www.mosis.com/cgi-bin/params/ami-c5/v3bm-params.txt
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Hänninen, I.K., Campos-Aguillón, C.O., Celis-Cordova, R., Snider, G.L. (2015). Design and Fabrication of a Microprocessor Using Adiabatic CMOS and Bennett Clocking. In: Krivine, J., Stefani, JB. (eds) Reversible Computation. RC 2015. Lecture Notes in Computer Science(), vol 9138. Springer, Cham. https://doi.org/10.1007/978-3-319-20860-2_11
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DOI: https://doi.org/10.1007/978-3-319-20860-2_11
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