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Energy Efficient Electrical Intra-Chip-Stack Communication

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Abstract

Through-silicon via (TSV) based 3D chip stacks provide many resources for compact and fast inter chip communication within a chip stack. They allow the design of highly integrated, heterogeneous, and compact systems with reduced overall power consumption, but very limited heat dissipation capability. This chapter presents a holistic packet-in packet-out point-to-point link architecture suitable for constructing a 3D network-on-chip (NoC) for connecting several processing elements within a Globally Asynchronous Locally Synchronous (GALS) design in a chip stack. This architecture has been implemented for long distance on-chip communication and for intra-chip-stack TSV based communication. After presenting a TSV behavioral description, models, hardware results, and a method for equivalent circuit parameter extraction, an energy efficient, capacitive coupling TSV transceiver is presented.

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Correspondence to Johannes Görner .

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Görner, J., Walter, D., Haas, M., Höppner, S. (2016). Energy Efficient Electrical Intra-Chip-Stack Communication. In: Elfadel, I., Fettweis, G. (eds) 3D Stacked Chips. Springer, Cham. https://doi.org/10.1007/978-3-319-20481-9_3

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  • DOI: https://doi.org/10.1007/978-3-319-20481-9_3

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