Skip to main content
SpringerLink
Log in

Standard Cell Compliance and Placement Co-Optimization

  • Chapter
Book cover Design for Manufacturability with Advanced Lithography

  • 1138 Accesses

Abstract

The TPL layout decomposition problem with conflict and stitch minimization has been studied extensively in the past few years [1–9], including the early work presented in Chaps. 2 and 3. However, most existing work suffers from one or more of the following drawbacks. (1) Because the TPL layout decomposition problem is NP-hard [3], most of the decomposers are based on approximation or heuristic methods, possibly leading to extra conflicts being reported. (2) For each design, since the library only contains a fixed number of standard cells, layout decomposition would contain numerous redundant works. For example, if one cell is applied hundreds of times in a single design, it would be decomposed hundreds of times during layout decomposition. (3) Successfully carrying out these decomposition techniques requires the input layouts to be TPL-friendly. However, since all these decomposition techniques are applied at a post-place/route stage, where all the design patterns are already fixed, they lack the ability to resolve some native TPL conflict patterns, e.g., four-clique conflicts.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Cork, C., Madre, J.-C., Barnes, L.: Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns. In: Proceedings of SPIE, vol. 7028 (2008)

    Google Scholar 

  2. Ghaida, R.S., Agarwal, K.B., Liebmann, L.W., Nassif, S.R., Gupta, P.: A novel methodology for triple/multiple-patterning layout decomposition. In: Proceedings of SPIE, vol. 8327 (2012)

    Google Scholar 

  3. Yu, B., Yuan, K., Zhang, B., Ding, D., Pan, D.Z.: Layout decomposition for triple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8 (2011)

    Google Scholar 

  4. Fang, S.-Y., Chen, W.-Y., Chang, Y.-W.: A novel layout decomposition algorithm for triple patterning lithography. In: ACM/IEEE Design Automation Conference (DAC), pp. 1185–1190 (2012)

    Google Scholar 

  5. Tian, H., Zhang, H., Ma, Q., Xiao, Z., Wong, M.D.F.: A polynomial time triple patterning algorithm for cell based row-structure layout. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 57–64 (2012)

    Google Scholar 

  6. Kuang, J., Young, E.F.: An efficient layout decomposition approach for triple patterning lithography. In: ACM/IEEE Design Automation Conference (DAC), pp. 69:1–69:6 (2013)

    Google Scholar 

  7. Yu, B., Gao, J.-R., Pan, D.Z.: Triple patterning lithography (TPL) layout decomposition using end-cutting. In: Proceedings of SPIE, vol. 8684 (2013)

    Google Scholar 

  8. Yu, B., Lin, Y.-H., Luk-Pat, G., Ding, D., Lucas, K., Pan, D.Z.: A high-performance triple patterning layout decomposer with balanced density. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 163–169 (2013)

    Google Scholar 

  9. Zhang, Y., Luk, W.-S., Zhou, H., Yan, C., Zeng, X.: Layout decomposition with pairwise coloring for multiple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 170–177 (2013)

    Google Scholar 

  10. Liebmann, L., Pietromonaco, D., Graf, M.: Decomposition-aware standard cell design flows to enable double-patterning technology. In: Proceedings of SPIE, vol. 7974 (2011)

    Google Scholar 

  11. Chen, T.-C., Cho, M., Pan, D.Z., Chang, Y.-W.: Metal-density-driven placement for CMP variation and routability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), 2145–2155 (2008)

    Article  Google Scholar 

  12. Hu, S., Shah, P., Hu, J.: Pattern sensitive placement perturbation for manufacturability. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(6), 1002–1006 (2010)

    Article  Google Scholar 

  13. Gupta, M., Jeong, K., Kahng, A.B.: Timing yield-aware color reassignment and detailed placement perturbation for bimodal cd distribution in double patterning lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8), 1229–1242 (2010)

    Article  Google Scholar 

  14. Gao, J.-R., Yu, B., Huang, R., Pan, D.Z.: Self-aligned double patterning friendly configuration for standard cell library considering placement. In: Proceedings of SPIE, vol. 8684 (2013)

    Google Scholar 

  15. Taghavi, T., Alpert, C., Huber, A., Li, Z., Nam, G.-J., Ramji, S.: New placement prediction and mitigation techniques for local routing congestion. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 621–624 (2010)

    Google Scholar 

  16. Ma, Q., Zhang, H., Wong, M.D.F.: Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In: ACM/IEEE Design Automation Conference (DAC), pp. 591–596 (2012)

    Google Scholar 

  17. Lin, Y.-H., Yu, B., Pan, D.Z., Li, Y.-L.: TRIAD: a triple patterning lithography aware detailed router. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 123–129 (2012)

    Google Scholar 

  18. NanGate FreePDK45 Generic Open Cell Library. http://www.si2.org/openeda.si2.org/projects/nangatelib (2008)

  19. Lucas, K., Cork, C., Yu, B., Luk-Pat, G., Painter, B., Pan, D.Z.: Implications of triple patterning for 14 nm node design and patterning. In: Proceedings of SPIE, vol. 8327 (2012)

    Google Scholar 

  20. Yuan, K., Pan, D.Z.: WISDOM: wire spreading enhanced decomposition of masks in double patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 32–38 (2010)

    Google Scholar 

  21. Fang, S.-Y., Chen, S.-Y., Chang, Y.-W.: Native-conflict and stitch-aware wire perturbation for double patterning technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5), 703–716 (2012)

    Article  MathSciNet  Google Scholar 

  22. Ghaida, R.S., Agarwal, K.B., Nassif, S.R., Yuan, X., Liebmann, L.W., Gupta, P.: Layout decomposition and legalization for double-patterning technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2), 202–215 (2013)

    Article  Google Scholar 

  23. Mentor Graphics.: Calibre verification user’s manual (2008)

    Google Scholar 

  24. Predictive Technology Model ver. 2.1. http://ptm.asu.edu (2008)

  25. Neapolitan, R., Naimipour, K.: Foundations of Algorithms. Jones & Bartlett Publishers, New Delhi (2010)

    Google Scholar 

  26. Vygen, J.: Algorithms for detailed placement of standard cells. In: IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), pp. 321–324 (1998)

    Google Scholar 

  27. Kahng, A.B., Tucker, P., Zelikovsky, A.: Optimization of linear placements for wirelength minimization with free sites. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 241–244 (1999)

    Google Scholar 

  28. Brenner, U., Vygen, J.: Faster optimal single-row placement with fixed ordering. In: IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), pp. 117–121 (2000)

    Google Scholar 

  29. Kahng, A.B., Reda, S., Wang, Q.: Architecture and details of a high quality, large-scale analytical placer. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 891–898 (2005)

    Google Scholar 

  30. Goto, S.: An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. Circuits Syst. 28(1), 12–18 (1981)

    Article  Google Scholar 

  31. Synopsys IC Compiler. http://www.synopsys.com (2013)

  32. Cadence SOC Encounter. http://www.cadence.com (2013)

Download references

Author information

Authors and Affiliations

  1. ECE Department, The University of Texas, Austin, TX, USA

    Bei Yu & David Z. Pan

Authors
  1. Bei Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. David Z. Pan
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Yu, B., Pan, D.Z. (2016). Standard Cell Compliance and Placement Co-Optimization. In: Design for Manufacturability with Advanced Lithography. Springer, Cham. https://doi.org/10.1007/978-3-319-20385-0_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-20385-0_4

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-20384-3

  • Online ISBN: 978-3-319-20385-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation