Abstract
Shrinking the feature size of very large scale integrated (VLSI) circuits with advanced lithography has been a holy grail for the semiconductor industry. However, the gap between manufacturing capability and the expectation of design performance becomes critical challenge for sub-32 nm technology nodes [1, 2]. Before addressing these challenges, we introduce some preliminaries of the current main-stream lithography system.
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Yu, B., Pan, D.Z. (2016). Introduction. In: Design for Manufacturability with Advanced Lithography. Springer, Cham. https://doi.org/10.1007/978-3-319-20385-0_1
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DOI: https://doi.org/10.1007/978-3-319-20385-0_1
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