Abstract
Network-on-Chip is gaining interest in these years thanks to its regular and scalable design. Several topologies have been proposed, and there is the need of a general framework for their test, validation and comparison. In this article a framework based on the OpenSPARC T2 processor is presented, where the NoC is used to replace the Cache Crossbar. With the introduction of protocol translators, it is possible to accomodate any NoC inside the T2. Processor regression tests can be used to validate the design and evaluate timing performance.
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Causapruno, G., Audero, A., Tota, S., Ruo Roch, M. (2016). A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. Lecture Notes in Electrical Engineering, vol 351. Springer, Cham. https://doi.org/10.1007/978-3-319-20227-3_13
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DOI: https://doi.org/10.1007/978-3-319-20227-3_13
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