Skip to main content
SpringerLink
Log in

Design Intelligence for Interconnection Realization in Power-Managed SoCs

  • Chapter
  • First Online:
Computational Intelligence in Digital and Network Designs and Applications

Abstract

In this chapter various intelligent techniques for modeling, design, automation, and management of on-chip interconnections in power-managed SoCs are described, including techniques that take into account various technological parameters such as crosstalk. Such intelligent techniques guarantee that the integrated interconnections, used in power-managed SoCs, are well-designed, energy-optimal, and meet the performance objectives in all the SoCs operating states.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
eBook
USD 16.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Martin, G.: Overview of the MPSoC design challenge. In: Proceedings of the 43rd Annual Design Automation Conference, July 2006

    Google Scholar 

  2. Horowitz, M., Indermaur, T., Gonzalez, R.: Low-power digital design. In: Symposium on low power electronics (1994)

    Google Scholar 

  3. Benini, L., Micheli, G.D.: Dynamic Power Management: Design Techniques and CAD Tools. Kluwer Academic Publishers, Massachusetts (1998)

    Book  MATH  Google Scholar 

  4. Burd, T.D., Brodersen, R.W.: Design issues for dynamic voltage scaling. In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, July 2000

    Google Scholar 

  5. Benini, L., Bogliolo, A., De Micheli, G.: A survey of design techniques for system-level dynamic power management. IEEE Trans. Very Large Scale Integr. Syst. 8(3), 299–316 (2000)

    Article  Google Scholar 

  6. Pontes, J., Moreira, M., Soares, R., Calazans, N.: Hermes-GLP: a GALS network on chip router with power control techniques. In: Proceedings of the International Symposium on VLSI (ISVLI) (2008)

    Google Scholar 

  7. Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D.H., Dwarkadas, S., Scott, M.L.: Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In: HPCA (2002)

    Google Scholar 

  8. Chen, G., Li, F., Kandemir, M., Irwin, M.: Reducing NoC energy consumption through compiler-directed channel voltage scaling. SIGPLAN Not. 41, 6, June (2006)

    Google Scholar 

  9. Li, F., Chen, G., Kandemir, M., Kolcu, I.: Profile-driven energy reduction in network-on-chips. SIGPLAN Not. 42, 6, June (2007)

    Google Scholar 

  10. Borkar, S.: Design challenges of technology scaling. IEEE Micro 19(4), 23–29 (1999)

    Article  Google Scholar 

  11. Zarkesh-Ha, P., Davis, J.A., Meindl, J.D.: Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 8, 649–659 (2000)

    Article  Google Scholar 

  12. Magen, N., Kolodny, A., Weiserm, U., Shamir, N.: Interconnect-power dissipation in a microprocessor. In: Proceedings of the International Workshop on System Level Interconnect Prediction, February (2004)

    Google Scholar 

  13. Lackey, D.E., Zuchowski, P.S., Bednar, T.R., Stout, D.W., Gould, S.W., Cohn, J.M.: Managing power and performance for system-on-chip designs using Voltage Islands. In: ICCAD (2002)

    Google Scholar 

  14. Semeraro, G., Albonesi, D.H., Dropsho, S.G., Magklis, G., Dwarkadas, S., Scott, M.L.: Dynamic frequency and voltage control for a multiple clock domain microarchitecture. ACM/IEEE International Symposium on Microarchitecture (2003)

    Google Scholar 

  15. Magklis, G., Scott, M.L., Semeraro, G., Albonesi, D.H., Dropsho, S.: Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In: ISCA (2003)

    Google Scholar 

  16. Bakoglu, H.B., Meindl, J.D.: Optimal interconnection circuits for VLSI. IEEE Trans. Electron Devices ED-32, 903–909 (1985)

    Google Scholar 

  17. Nalamalpu, A., Burleson, W.: A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power. In: IEEE ASIC/SOC Conference, September (2001)

    Google Scholar 

  18. Chen, G., Friedman, E.G.: Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. In: IEEE TVLSI, February (2006)

    Google Scholar 

  19. Kaul, H., Sylvester, D., Blaauw, D., Mudge, T., Austin, T.: DVS for on-chip bus designs based on timing error correction. DATE, March (2005)

    Google Scholar 

  20. Banerjee, K., Mehrotra, A.: A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 49(11), 2001–2007 (2002)

    Google Scholar 

  21. Nalamalpu, A., Srinivasan, S., Burleson, W.P.: Boosters for driving long onchip interconnects-design issues, interconnect synthesis, and comparison with repeaters. IEEE Trans Comput.-Aided Des. 21(1), 50–62 (2002)

    Article  Google Scholar 

  22. Alpert, C., Devgan, A., Quay, S.: Buffer insertion for noise and delay optimization. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18(11), 1633–1645 (1999)

    Article  Google Scholar 

  23. van Ginneken, L.P.P.P.: Buffer placement in distributed RC-tree networks for minimal elmore delay. In: Proceedings of the International Symposium Circuits System (ISCAS), pp. 865–868 (1990)

    Google Scholar 

  24. Adler, V., Friedman, E.G.: Repeater design to reduce delay and power in resistive interconnect. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 45(5), 607–616 (1998)

    Article  Google Scholar 

  25. Ismail, Y.I., Friedman, E.G.: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 8(2), 195–206 (2000)

    Article  Google Scholar 

  26. Akl, C.J., Bayoumi, M.A.: Reducing interconnect delay uncertainty via hybrid polarity repeater insertion. IEEE Trans. Very Large Scale Integr. Syst. 16(9), 1230–1239 (2008)

    Article  Google Scholar 

  27. Zhai, B., Blaauw, D., Sylvester, D., Flautner, K.: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. Trans. VLSI 13(11), 1239–1252 (2005)

    Article  Google Scholar 

  28. Kursun, V., Friedman, E.G.: Multi-Voltage CMOS Circuit Design. Wiley, West Sussex (2006)

    Book  Google Scholar 

  29. Sinha, A., Chandrakasan, A.P.: Dynamic power management in wireless sensor networks. IEEE Des. Test 18(2), 62–74 (2001)

    Article  Google Scholar 

  30. Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: An interconnect-aware delay model for dynamic voltage scaling in nm technologies. In: GLSVLSI (2009)

    Google Scholar 

  31. Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: Repeater design for power-managed VLSI. Submitted to GLSVLSI (2011)

    Google Scholar 

  32. Zarrabi, H., Al-Khalili, A.J., Savaria, Y.: An interconnect-aware dynamic voltage scaling scheme for DSM VLSI. In: ISCAS, May 2010

    Google Scholar 

  33. Sakurai, T.: Approximation of wiring delay in MOS-FET LSI. IEEE J. Solid-State Circuits SC-18(4), 418–426 (1983)

    Google Scholar 

  34. Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall, Upper Saddle River (2003)

    Google Scholar 

  35. Elmore, W.C.: The transient response of damped linear networks with particular regard to wide-band amplifiers. J. Appl. Phys. 19(1), 55–63 (1948)

    Article  Google Scholar 

  36. Cong, J., Pan, D.Z.: Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits 49(11), 1671–1677 (2002)

    Google Scholar 

  37. Zarrabi, H., Saaied, H., Al-Khalili, A.J., Savaria, Y.: Zero skew differential clock distribution network. In: International Symposium on Circuit and Systems (ISCAS), May 2006

    Google Scholar 

  38. Zhang, J., Friedman, E.G.: Decoupling technique and crosstalk analysis of coupled RLC interconnects. In: Proceedings of the IEEE International Symposium on Circuits and Systems II, pp. 521–524 , May 2004

    Google Scholar 

  39. Kahng, A.B., Muddu, S., Sarto, E.: On switch factor based analysis of coupled RC interconnects. In: Proceedings of the Design Automation Conference, June 2000

    Google Scholar 

  40. Pileggi, L.: Coping with RC(L) interconnect design headaches. IEEE ICCAD Tutorial, November 1995

    Google Scholar 

  41. Yee, G., Chandra, R., Ganesan, V., Sechen, C.: Wire delay in the presence of crosstalk. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December 1997

    Google Scholar 

  42. Duan, C., LaMeres, B.J., Khatri, S.: On and Off-chip Cross-talk Avoidance in VLSI Designs. Springer, New York (2010)

    Book  Google Scholar 

  43. Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45nm design exploration. IEEE International Symposium on Quality Electronic Design (ISQED) (2006)

    Google Scholar 

  44. International Technology Roadmap for Semiconductors: http://www.itrs.net

  45. Berkeley Predictive Technology Model. http://www-device.eecs.berkeley.edu/ptm

  46. Li, X.C., Mao, J.F., Huang, H.F., Liu, Y.: Global interconnect width and spacing optimization for latency, bandwidth and power dissipation. IEEE Trans. Electron. Devices 52, 2272–2279 (2005)

    Article  Google Scholar 

  47. Wang, A., Calhoun, B.H., Chandrakasan, A.P.: Sub-Threshold Design for Ultra Low-Power Systems. Springer, New York (2006)

    Google Scholar 

  48. Wang, A., Chandrakasan, A.P.: A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid-State Circuits 40(1), 310–319 (2005)

    Article  MATH  Google Scholar 

  49. Calhoun, H.B., Ryan, J., Khanna, S., Putic, M., Lach, J.: Flexible circuits and architectures for ultra low power. Proc. IEEE 98(2), 267–282 (2010)

    Article  Google Scholar 

  50. Chandrakasan, A.P., Daly, D.C., Finchelstein, D.F., Kwong, J., Ramadass, Y.K., Sinangil, M.E., Sze, V., Verma, N.: Technologies for ultradynamic voltage scaling. Proc. IEEE 98(2), 191–214 (2010)

    Article  Google Scholar 

  51. Forestier, A., Stan, M.R.: Limits to voltage scaling from the low power perspective. In: Symposium on Integrated Circuits and Systems Design, September 2000

    Google Scholar 

  52. Macchiarulo, L., Macii, E., Poncino, M.: Low-Energy encoding for deep-submicron address buses. In: ISLPED (2001)

    Google Scholar 

  53. Kalyan, T.V., Mutyam, M., Rao, P.V.: Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design. In: International Conference on VLSI Design (2008)

    Google Scholar 

  54. Ghoneima, M., Ismail, Y., Khellah, M.M., Tschanz, J., De, V.: Serial-link bus: a low-power on-chip bus architecture. Trans. Circuits Sys. Part I (2009)

    Google Scholar 

  55. Sotiriadis,, P.P., Chandrakasan, A.P.: A bus energy model for deep submicron technology, IEEE Trans. Very Large Scale Integr. Syst., June 2002

    Google Scholar 

  56. Sotiriadis, P., Chandrakasan, A.P.: Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model, IEEE Trans. Circuits Syst., pp. 1280–1295, October 2003

    Google Scholar 

  57. Deogun, H., Rao, R.M., Sylvester, D., Brown, R., Nowka, K.: Dynamically pulsed MTCMOS with bus encoding for total power and crosstalk minimization. In: IEEE International Symposium on Quality Electronic Design, pp. 88–93 (2005)

    Google Scholar 

  58. Benini, L., De Micheli, G., Macii, E., Sciuto, D., Silvano, S.: Address bus encoding techniques for system-level power optimization, In: Proceedings of the Conference on Design, Automation and Test in Europe, February 1998

    Google Scholar 

  59. Suresh, D.C., Agrawal, B., Yang, J., Najjar, W.A.: Tunable and energy efficient bus encoding techniques, IEEE Trans. Comput. (2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of ECE, Concordia University, Montreal, Canada

    Houman Zarrabi & A. J. Al-Khalili

  2. Department of EEE, Ecole Polytechnique de Montreal, Montreal, Canada

    Yvon Savaria

Authors
  1. Houman Zarrabi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. A. J. Al-Khalili
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yvon Savaria
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Houman Zarrabi .

Editor information

Editors and Affiliations

  1. Department of Electronics, ENET’Com, University of Sfax, Sfax, Tunisia

    Mourad Fakhfakh

  2. Department of Electronics, INAOE, Tonantzintla, Mexico

    Esteban Tlelo-Cuautle

  3. Laboratoire LiSSi (EA 3956), Université Paris-Est Créteil, Vitry sur Seine, France

    Patrick Siarry

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Zarrabi, H., Al-Khalili, A.J., Savaria, Y. (2015). Design Intelligence for Interconnection Realization in Power-Managed SoCs. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Digital and Network Designs and Applications. Springer, Cham. https://doi.org/10.1007/978-3-319-20071-2_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-20071-2_3

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-20070-5

  • Online ISBN: 978-3-319-20071-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation