Abstract
The theory and practice of applying a neural network model and learning algorithm—Independent Component Analysis (ICA)—to the online adaptive calibration of analog-to-digital converters (ADCs) is covered in this chapter. Exploiting the independence between the input signal and an injected pseudorandom bit sequence (PRBS), the technique attempts to blindly separate the two in the digital conversion output, and while doing so, an equivalent model of the ADC non-idealities is identified, resulting in the subsequent linearization of the conversion process. The ICA framework offers new signal-processing insights into the widely used correlation-based error-parameter identification method for the background calibration of multistage ADCs. In addition, it provides a useful technique to minimize the analog overhead associated with the calibration by simultaneously identifying multiple model parameters using a single PRBS, improving the efficiency and potentially the application regime of the online calibration approach for data converters.
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- 1.
One can imagine this by sliding the threshold at zero to the left or right while confining it in between the two parallel residue segments with a slope of two.
- 2.
As quantization can be understood as division, the 1.5-bit topology is actually a realization of the Sweeny–Robertson–Tocher (SRT) fast division algorithm well known in computer arithmetic.
- 3.
For simplicity and better clarity, we will drop the constant scaling factor V R in all the equations from this point onward.
- 4.
The reported simulation results correspond to a sinusoidal input waveform in this example. The convergence time and learning accuracy do not seem to depend on the input waveform much, as long as it is busy and occupies most of the input range. The readers are referred to [6] for a more detailed discussion on this.
References
S.H. Lewis, H.S. Fetterman, G.F. Gross Jr., R. Ramachandran, T.R. Viswanathan, A 10-b 20-MS/s analog-to-digital converter. IEEE J. Solid State Circuits 27, 351–358 (1992)
B. Ginetti, P.G.A. Jespers, A. Vandemeulebroecke, A CMOS 13-b cyclic RSD A/D converter. IEEE J. Solid State Circuits 27, 957–964 (1992)
F. Kuttner, A 1.2 V 10b 20 MS/s non-binary SAR ADC in 0.13 μm CMOS, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 176–177, 2002
C.-C. Liu et al., A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 386–387, 2010
W. Liu et al., A 12b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 380–381, 2010
Y. Chiu et al., Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I 51, 38–46 (2004)
C. Tsang et al., Background ADC calibration in digital domain, in Proc. IEEE Custom Integrated Circuits Conf., pp. 301–304, 2008
Y. Chiu, Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters, in IEEE Int. Conf. Solid-State and Integrated-Circuit Tech., pp. 1905−1908, 2008
M.K. Mayes, S.W. Chin, A 200-mW, 1-MS/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller. IEEE J. Solid State Circuits 31, 1862–1872 (1996)
A. Wiesbauer, G.C. Temes, Adaptive compensation of analog circuit imperfections for cascaded sigma-delta modulators, in Proc. Asilomar Conf. Circuits, Systems and Computers, vol. 2, pp. 1073–1077, 1996
C. Petrie, M. Miller, A background calibration technique for multibit delta-sigma modulators, in Proc. IEEE Int. Sym. Circuits and Systems, vol. 2, pp. 29–32, 2000
T. Sun, A. Wiesbauer, G.C. Temes, Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs, in Proc. IEEE Int. Sym. Circuits and Systems, vol. 1, pp. 405–407, 1998
P. Kiss et al., Adaptive digital correction of analog errors in MASH ADC’s—Part II: correction using test-signal injection. IEEE Trans. Circuits Syst. II 47, 629–638 (2000)
D. Fu, K.C. Dyer, S.H. Lewis, P.J. Hurst, A digital back-ground calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid State Circuits 33, 1904–1911 (1998)
J. Ming, S.H. Lewis, An 8 b 80 Msample/s pipelined ADC with background calibration, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 42–43, 2000
E.J. Siragusa, I. Galton, Gain error correction technique for pipelined analogue-to-digital converters. Electron. Lett. 36, 617–618 (2000)
I. Galton, Digital cancellation of D/A converter noise in pipelined A/D converters. IEEE Trans. Circuits Syst. II 47, 185–196 (2000)
P.C. Yu et al., A 14b 40 MSample/s pipelined ADC with DFCA, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 136–137, 2001
E. Siragusa, I. Galton, A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. IEEE J. Solid State Circuits 39, 2126–2138 (2004)
H.-C. Liu, Z.-M. Lee, J.-T. Wu, A 15b 20 MS/s CMOS pipelined ADC with digital background calibration, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 454–455, 2004
K. Nair, R. Harjani, A 96 dB SFDR 50 MS/s digitally enhanced CMOS pipeline A/D converter, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 456–457, 2004
R. Massolini, G. Cesura, R. Castello, A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC. IEEE Trans. Circuits Syst. II 53, 389–393 (2006)
Y.-S. Shu, B.-S. Song, A 15b linear, 20 MS/s, 1.5b/stage pipelined ADC digitally calibrated with signal-dependent dithering, in IEEE Sym. VLSI Circuits, Dig. Tech. Papers, pp. 218–219, 2006
B. Murmann, B. Boser, A 12b 75 MS/s pipelined ADC using open-loop residue amplification, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 328–329, 2003
J. Keane et al., Background interstage gain calibration technique for pipelined ADCs. IEEE Trans. Circuits Syst. I 52, 32–43 (2005)
J. Li, U.-K. Moon, Background calibration techniques for multistage pipelined ADC’s with digital redundancy. IEEE Trans. Circuits Syst. II 50, 531–538 (2003)
A. Panigada, I. Galton, Digital background correction of harmonic distortion in pipelined ADCs. IEEE Trans. Circuits Syst. I 53, 1885–1895 (2006)
A. Panigada, I. Galton, A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 162–163, 2009
R. Jewett, K. Poulton, K.-C. Hsieh, J. Doernberg, A 12b 128 MS/s ADC with 0.05LSB DNL, in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 138–139, 1997
H.S. Fetterman, D.G. Martin, D.A. Rich, CMOS pipelined ADC employing dither to improve linearity, in Proc. IEEE Custom Integrated Circuits Conf., pp. 109–112, 1999
J. McNeill, M.C.W. Coln, B.J. Larivee, “Split ADC” architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE J. Solid State Circuits 40, 2437–2445 (2005)
J.A. McNeill, S. Goluguri, A. Nair, Split ADC digital background correction of open loop residue amplifier non linearity errors in a 14b pipelined ADC, in Proc. IEEE Int. Symp. Circuits and Systems, pp. 1237–1240, 2007
I. Ahmed, D. Johns, An 11-bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage. IEEE J. Solid State Circuits 43, 1626–1637 (2008)
L.-H. Hung, T.-C. Lee, A split-based digital background calibration technique in pipelined ADCs. IEEE Trans. Circuits Syst. II 56, 855–859 (2009)
L. Ding et al., A 13-bit 60 MS/s split pipelined ADC with background gain and mismatch error calibration, in IEEE Asian Solid-State Circuits Conf., pp. 77–80, 2013
B. Peng, H. Li, P. Lin, Y. Chiu, An offset double conversion technique for digital calibration of pipelined ADCs. IEEE Trans. Circuits Syst. II 57, 961–965 (2010)
W. Liu, P. Huang, Y. Chiu, A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration. IEEE J. Solid State Circuits 46, 2661–2672 (2011)
J. Hérault, C. Jutten, Space or time adaptive signal processing by neural network models, in Proc. Neural Networks for Computing, vol. 151, pp. 206–211, 1986
J.-F. Cardoso, Source separation using higher order moments, in Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. 2109–2112, 1989
E.A. Vittoz, X. Arreguit, CMOS integration of Hérault-Jutten cells for separation of sources, in Analog VLSI Implementation of Neural Systems, ed. by C. Mead, M. Ismail (Springer, Berlin, 1989)
C. Jutten, J. Hérault, Blind separation of sources, part I: an adaptive algorithm based on neuromimetic architecture. Signal Process. 24, 1–10 (1991)
P. Comon, C. Jutten, J. Hérault, Blind separation of sources, part II: problems statement. Signal Process. 24, 11–20 (1991)
E. Sorouchyari, Blind separation of sources, part III: stability analysis. Signal Process. 24, 21–29 (1991)
G. Burel, Blind separation of sources: a nonlinear neural algorithm. Neural Netw. 5, 937–947 (1992)
A. Cichocki, R. Unbehauen, Robust neural networks with on-line learning for blind identification and blind separation of sources. IEEE Trans. Circuits Syst. 43, 894–906 (1996)
S.-I. Amari, A. Cichocki, Adaptive blind signal processing—neural network approaches. Proc. IEEE 86, 2026–2048 (1998)
H.B. Barlow, Unsupervised learning. Neural Comput. 1, 295–311 (1989)
J.-F. Cardoso, P. Comon, Independent Component Analysis: a survey of some algebraic methods, in Proc. IEEE Int. Sym. Circuits and Systems, vol. 2, pp. 93–96, 1996
S. Haykin, Adaptive Filter Theory, 3rd edn. (Prentice Hall, Upper Saddle River, 1996)
A. Hyvärinen, J. Karhunen, E. Oja, Independent Component Analysis (Wiley, New York, 2001)
W. Liu, P. Huang, Y. Chiu, A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration, in Proc. IEEE Custom Integrated Circuits Conf., pp. 1–4, 2012
Y. Zhou, Y. Chiu, Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC, in Proc. IEEE Int. Midwest Symp. Circuits and Systems, pp. 677–680, 2013
S.-C. Lee, Y. Chiu, Digital calibration of nonlinear memory errors in sigma-delta modulators. IEEE Trans. Circuits Syst. I 57, 2462–2475 (2010)
S.-C. Lee, Y. Chiu, Digital calibration of capacitor mismatch in sigma-delta modulators. IEEE Trans. Circuits Syst. I 58, 690–698 (2011)
S.-C. Lee, Y. Chiu, A 15-MHz bandwidth 1-0 MASH ΣΔ ADC with nonlinear memory error calibration achieving 85-dBc SFDR. IEEE J. Solid State Circuits 49, 695–707 (2014)
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Chiu, Y. (2015). Digital Adaptive Calibration of Data Converters Using Independent Component Analysis. In: Pfander, G. (eds) Sampling Theory, a Renaissance. Applied and Numerical Harmonic Analysis. Birkhäuser, Cham. https://doi.org/10.1007/978-3-319-19749-4_14
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DOI: https://doi.org/10.1007/978-3-319-19749-4_14
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