Abstract
This work evaluates implementation efficiency of different cryptographic algorithms in selected hardware organizations and in different FPGA devices. The tests included AES symmetric cipher and two more contemporary hash algorithms: Salsa20 and Keccak-f[400] permutation function. Each algorithm was realized in hardware in five organizations: the basic iterative one, two with the loop unrolled and two with the loop unrolled and pipelined, then automatically implemented in two popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. Results of 30 test cases allowed for evaluation of particular strengths and weaknesses of the ciphers, the organizations and the FPGA architectures. In particular, the evaluation took into account implementation efficiency offered by the two device families, scalability of the ciphers with the loop unrolling factor and specific routing problems which came out in some configurations.
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Sugier, J. (2015). Popular FPGA Device Families in Implementation of Cryptographic Algorithms. In: Zamojski, W., Mazurkiewicz, J., Sugier, J., Walkowiak, T., Kacprzyk, J. (eds) Theory and Engineering of Complex Systems and Dependability. DepCoS-RELCOMEX 2015. Advances in Intelligent Systems and Computing, vol 365. Springer, Cham. https://doi.org/10.1007/978-3-319-19216-1_46
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DOI: https://doi.org/10.1007/978-3-319-19216-1_46
Publisher Name: Springer, Cham
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