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Three-Dimensional FPGAs: Configuration and CAD Development

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Three-Dimensional Design Methodologies for Tree-based FPGA Architecture

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 350))

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Abstract

The primary focus of this chapter is to demonstrate a 3D integration scheme to partition and optimize the multilevel programmable interconnect network of Tree-based FPGA based on Butterfly-Fat-Tree network topology, where TSVs are incorporated in active layers of the 3D chip. This chapter describes the details of the architecture of 3D FPGAs and state-of-the-art 3D technology for Mesh-based FPGAs. To take advantage of 3D integrated circuits, it should be investigated how FPGA should be physically partitioned into different active layers. Proper physical partitioning has a great impact on the performance improvement of the system. This chapter discuss different partitioning schemes and design techniques and associated 3D CAD tools of 3D FPGAs.

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Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, School of Engineering, American University in Dubai, Dubai, United Arab Emirates

    Vinod Pangracious

  2. Flexras Technologies, Biocitech, Romainville, France

    Zied Marrakchi

  3. University of Pierre and Marie Curie, Paris VI, Paris, France

    Habib Mehrez

Authors
  1. Vinod Pangracious
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  2. Zied Marrakchi
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  3. Habib Mehrez
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Correspondence to Vinod Pangracious .

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Pangracious, V., Marrakchi, Z., Mehrez, H. (2015). Three-Dimensional FPGAs: Configuration and CAD Development. In: Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Lecture Notes in Electrical Engineering, vol 350. Springer, Cham. https://doi.org/10.1007/978-3-319-19174-4_5

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  • DOI: https://doi.org/10.1007/978-3-319-19174-4_5

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-19173-7

  • Online ISBN: 978-3-319-19174-4

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