Abstract
The paper presents the advantage of the Ultra-thin body and buried-oxide (BOX) (UTTB) fully depleted silicon-on-insulator (FDSOI) as an enabling transistor technology through effective back-gate biasing schemes to overcome the challenges that arises from downscaling bulk CMOS technology for low power and high-speed design tradeoff. The effects of the back-gate bias methodologies that can vary or modulate the substrate bias to adapt the transistor’s threshold voltage are detailed. The design schemes that can be used with this technology are described to illustrate their applications with UTTB FDSOI transistor.
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Acknowledgments
The research leading to these results has received funding from the Fundação para a Ciência e Tecnologia and the ENIAC JU (THINGS2DO–GA n. 621221).
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© 2015 Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Dghais, W., Rodriguez, J. (2015). UTTB FDSOI Back-Gate Biasing for Low Power and High-Speed Chip Design. In: Mumtaz, S., Rodriguez, J., Katz, M., Wang, C., Nascimento, A. (eds) Wireless Internet. WICON 2014. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 146. Springer, Cham. https://doi.org/10.1007/978-3-319-18802-7_16
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DOI: https://doi.org/10.1007/978-3-319-18802-7_16
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