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Trends in 3D Integrated Circuit (3D-IC) Testing Technology

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Three-Dimensional Integration of Semiconductors

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Abstract

Since the 3D integrated circuit (3D-IC) consists of several dies that are connected by the huge number of through-silicon vias (TSVs), the yield of a 3D-IC makes an impact on the chip cost. Therefore, development of testing technology for 3D-IC becomes essential for reducing the manufacturing cost of 3D-IC. In this chapter, we describe the testing technologies for 3D-IC. In Sect. 8.1, we marshal the issues that must be handled in the 3D-IC testing. From Sects. 8.2 to 8.4, we introduce the outlining of the proposed 3D-IC testing technologies in so far. From Sects. 8.5 to 8.7, we provide the 3D-IC testing technologies that are proposed by our research group in Japan.

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Acknowledgments

The authors would like to thank Mr. T. Konishi and Mr. S. Umezu, The University of Tokushima, for their experimental evaluation. This work was supported by VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Synopsys, Inc, Cadence Design Systems, Inc, and Mentor Graphics, Inc. The IC chip in this study has been designed in the chip fabrication program of VDEC, University of Tokyo, in collaboration with Rohm Corporation and Toppan Printing Corporation.

Author information

Authors and Affiliations

  1. Ehime University, Ehime, Japan

    Senling Wang & Yoshinobu Higami

  2. Fujitsu Limited, Kanagawa, Japan

    Shuichi Kameyama

  3. Computer Science, Graduate School of Science and Engineering, Ehime University, Ehime, Japan

    Hiroshi Takahashi

  4. The University of Tokushima, Tokushima, Japan

    Hiroyuki Yotsuyanagi & Masaki Hashizume

  5. National Taiwan University of Science and Technology, Taipei, Taiwan (R.O.C.)

    Shyue-Kung Lu

  6. Florida Atlantic University, Boca Raton, FL, USA

    Zvi Roth

Authors
  1. Hiroshi Takahashi
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  2. Senling Wang
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  3. Shuichi Kameyama
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  4. Yoshinobu Higami
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  5. Hiroyuki Yotsuyanagi
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  6. Masaki Hashizume
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  7. Shyue-Kung Lu
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  8. Zvi Roth
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Corresponding author

Correspondence to Hiroshi Takahashi .

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Editors and Affiliations

  1. Department of Chemical Engineering, Osaka Prefecture University, Osaka, Japan

    Kazuo Kondo

  2. AIST , Tsukuba, Ibaraki, Japan

    Morihiro Kada

  3. Toshiba Corporation, Oita, Japan

    Kenji Takahashi

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Takahashi, H. et al. (2015). Trends in 3D Integrated Circuit (3D-IC) Testing Technology. In: Kondo, K., Kada, M., Takahashi, K. (eds) Three-Dimensional Integration of Semiconductors. Springer, Cham. https://doi.org/10.1007/978-3-319-18675-7_8

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