Abstract
This chapter explores particular advantage(s) of FPGAs for investigating nonlinear dynamics—realization of time delayed chaotic systems. These advantages are the availability of on-chip memory and the fact that generate statements in VHDL can be used to elegantly implement arbitrary (limited by on-chip memory and the number of FPGA logic elements) length delay chains. We will also explore synchronization applications in chaotic DDEs using the FPGA.
Keywords
- FPGA Logic Elements
- FPGA Realization
- Coupling Function
- Investigate Chaos Synchronization
- Chaotic Systems Synchronization
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Valli et al. Synchronization in Coupled Ikeda Delay Systems: Experimental Observations using FPGAs [7]
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References
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Wolfson (2013) WM8731 datasheet, Available via DIALOG. http://www.wolfsonmicro.com/products/audio_hubs/WM8731/ Accessed 4 Oct 2013
Acknowledgments
Many thanks to our colleagues at the Vellore Institute of Technology, Vellore, India for working with us on the synchronization experiments. Specifically, Ph.D. candidate Ms. Valli, Professors Ganesan and Subramanian have been extremely helpful.
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Appendices
Problems
5.1
Consider the Ikeda DDE:
\(\mu =6, \tau =1,\alpha =1\).
Perform a ModelSim simulation of the system above.
5.2
One approach to speed up the synthesis procedure is to minimize the number of delays by increasing the sampling frequency of the system. Explore this approach by increasing the sampling frequency for, say, the Ikeda system.
5.3
One of the earliest and most widely studied DDE is the Mackey-Glass equation [6], shown in Eq. (5.15).
Parameters for chaos: \(a=3, b=1,c=7,\tau =3\) [6]. Implement the equation on the FPGA.
5.4
Implement the antisymmetric piecewise-linear DDE [6], shown in Eq. (5.16) on the FPGA. Use \(\tau =3\).
5.5
Implement the asymmetric piecewise-linear DDE [6], shown in Eq. (5.17) on the FPGA. Use \(\tau =1.8\).
5.6
Explore the synchronization schemes discussed in Sect. 5.4 using the DDEs from problems 5.3, 5.4 and 5.5.
5.7
In Eq. (5.18), the time derivative depends on the average value of a function for time lags of \(x_s\) from \(s=0\text { to } \tau \). Implement the equation on an FPGA, using \(\tau =3\).
5.8
Investigate bifurcation mechanisms in any of the DDEs from this chapter.
Lab 5: The Lang-Kobayashi Chaotic Delay Differential Equation
Objective: Simulate and physically realize the Lang-Kobayashi (L-K) chaotic DDEÂ [2]
Theory: Notice that Eq. (5.19) is in the complex domain. However we can separate the real and imaginary parts by writing \(E(t)=\rho (t)e^{i\theta (t)}\) in Eq. (5.19) to obtain Eqs. (5.20) and (5.21).
Verify that one can indeed obtain Eqs. (5.20) and (5.21) from Eq. (5.19).
Lab Exercise:
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Muthuswamy, B., Banerjee, S. (2015). Chaotic DDEs: FPGA Examples and Synchronization Applications. In: A Route to Chaos Using FPGAs. Emergence, Complexity and Computation, vol 16. Springer, Cham. https://doi.org/10.1007/978-3-319-18105-9_5
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DOI: https://doi.org/10.1007/978-3-319-18105-9_5
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