Chaotic ODEs: FPGA Examples

Abstract

In this chapter, we will focus on realizing chaotic systems on an FPGA. We will first show a simple numerical method for specifying chaotic systems on the FPGA and then realize the Lorenz system. We will then illustrate the complete FPGA design process of functional simulation, in-system debugging and physical implementation. In order to illustrate the robustness of FPGAs, we will conclude this chapter by realizing a chaotic system with a hyperbolic tangent nonlinearity.

FPGA realization of the chaotic attractor from the Highly Complex Attractor system [10]

Appendices

Problems

3.1

Experiment with the sampling frequency and fixed point representation for the highly complex attractor system.

3.2

Reconsider the Chua system (Eqs. 1.82, 1.83 and 1.84), repeated below for convenience.

$$\begin{aligned} \dot{x}&=\alpha [y- x - m_1 x - \frac{1}{2}\left( m_0-m_1\right) \left( |x+1|-|x-1|\right) ] \end{aligned}$$

(3.16)

$$\begin{aligned} \dot{y}&=x-y+z \end{aligned}$$

(3.17)

$$\begin{aligned} \dot{z}&=-\beta y \end{aligned}$$

(3.18)

$m_0,m_1,\alpha ,\beta \in \mathbb {R}$ are parameters of the system. Use $m_0=\frac{-8}{7},m_1=\frac{-5}{7},\alpha =15.6,\beta =25.58$ to perform a discrete simulation and then realize the system on the FPGA.

3.3

Simulate and implement Sprott’s jerky chaotic system shown in Eqs. (3.19), (3.20) and (3.21).

$$\begin{aligned} \dot{x}&=-2y \end{aligned}$$

(3.19)

$$\begin{aligned} \dot{y}&=x+z^2 \end{aligned}$$

(3.20)

$$\begin{aligned} \dot{z}&=1+y-2z \end{aligned}$$

(3.21)

3.4

Simulate and implement the R$\ddot{\text {o}}$ssler system in Eqs. (3.22), (3.23) and (3.24).

$$\begin{aligned} \dot{x}&=-y-z \end{aligned}$$

(3.22)

$$\begin{aligned} \dot{y}&=x+\alpha y \end{aligned}$$

(3.23)

$$\begin{aligned} \dot{z}&=\beta +z(x-\gamma ) \end{aligned}$$

(3.24)

$\alpha ,\beta ,\gamma \in \mathbb {R}$ are parameters of the system. Use $\alpha =0.1,\beta =0.1,\gamma =14$.

3.5

Simulate and implement the hyperchaotic L$\ddot{\text {u}}$ system [3] in Eqs. (3.25), (3.26), (3.27) and (3.28).

$$\begin{aligned} \dot{x}&=a(y-x)+u \end{aligned}$$

(3.25)

$$\begin{aligned} \dot{y}&=-xz+cy \end{aligned}$$

(3.26)

$$\begin{aligned} \dot{z}&=xy-bz \end{aligned}$$

(3.27)

$$\begin{aligned} \dot{u}&=xz+du \end{aligned}$$

(3.28)

Parameter values are: $a=36,b=3,c=20,d=1.3$. Initial conditions are (1, 2, 3, 4). Note that since we have a four-dimensional system and for the parameters chosen we have a value of hyperchaos. When we realize this system on the FPGA, we have to make sure that we output all four state variables via the DAC on the audio codec.

3.6

We could make a refinement on the simple forward-Euler numerical method for solving chaotic differential equations by considering the fourth-order RK method shown in Eqs. (3.29)–(3.33) [11].

$$\begin{aligned} \mathbf {k}_1&= \mathbf {F}(\mathbf {x}_t)\delta t \end{aligned}$$

(3.29)

$$\begin{aligned} \mathbf {k}_2&=\mathbf {F}\left( \mathbf {x}_t+\frac{\mathbf {k}_1}{2}\right) \delta t \end{aligned}$$

(3.30)

$$\begin{aligned} \mathbf {k}_3&=\mathbf {F}\left( \mathbf {x}_t+\frac{\mathbf {k}_2}{2}\right) \delta t \end{aligned}$$

(3.31)

$$\begin{aligned} \mathbf {k}_4&=\mathbf {F}\left( \mathbf {x}_t+\mathbf {k}_3\right) \delta t \end{aligned}$$

(3.32)

$$\begin{aligned} \mathbf {x}_{t+\delta t}&= \mathbf {x}_t+\frac{\mathbf {k}_1}{6}+\frac{\mathbf {k}_2}{3} + \frac{\mathbf {k}_3}{3} + \frac{\mathbf {k}_4}{6} \end{aligned}$$

(3.33)

Implement Eqs. (3.29)–(3.33) on the FPGA. A maximum step size of $\delta t=0.1$ is more than adequate for most cases because the natural period of oscillation is typically less than 1 rad per second when the parameters are of order unity, and thus there is the order of $\frac{2\pi }{\delta t} \approx 63$ iterations per cycle [11]. Using this idea, determine an appropriate step size ($\Delta t$) and sampling count for the FPGA realization. Test your algorithm by implementing the circulant chaotic system [11] on the FPGA.

$$\begin{aligned} \dot{x}&=-ax+by-y^3 \end{aligned}$$

(3.34)

$$\begin{aligned} \dot{y}&=-ay+bz-z^3 \end{aligned}$$

(3.35)

$$\begin{aligned} \dot{z}&=-az+bx-x^3 \end{aligned}$$

(3.36)

Parameters are: $a=1, b=4$. Initial conditions are (0.4, 0, 0). Note that the online reference design for this chapter has an Euler’s method realization of the circulant chaotic system. Compare your RK realization to the Euler realization.

3.7

Perform a functional simulation of the simple combinational logic design from Sect. 2.3.2.1 (listing 2.1). Note that although a functional simulation is “overkill” for this design, this problem should help you understand the nuances of ModelSim by using a very simple example for simulation.

3.8

Perform a functional simulation of the generic n-bit ripple carry adder from Sect. 2.3.2.3.

3.9

Perform a functional simulation of the i$^2$c design from Sect. 2.3.3.

3.10

Design and verify the SignalTap waveforms for the PLL based design in Sect. 3.5.1. Also add a global asynchronous reset.

Lab 3 : ModelSim Simulation, In-System Debugging and Physical Realization of the Muthuswamy-Chua System

Objective: Simulate and physically realize the Muthuswamy-Chua [6, 8, 13] system.

Theory: The Muthuswamy-Chua system models a linear inductor, linear capacitor and memristor in series (or parallel). In this book, we will use the original series version whose system equations are Eqs. (3.37)–(3.39) [8].

$$\begin{aligned} \dot{v}_C&=\frac{i_L}{C} \end{aligned}$$

(3.37)

$$\begin{aligned} \dot{i}_L&=\frac{-1}{L}\left( v_C+R(z)i_L\right) \end{aligned}$$

(3.38)

$$\begin{aligned} \dot{z}&=f(z,i_L) \end{aligned}$$

(3.39)

Lab Exercise:

Simulate, verify using SignalTap and hence implement Eqs. (3.37)–(3.39) for the following parameters and functions: $C=1, L=3, R(z)=\beta (z^2-1), f(z,i_L)= -i_L -\alpha z + z i_L, \beta = 1.5, \alpha = 0.6$. Initial conditions are: (0.1, 0, 0.1). For the simulation, please check the output from the audio codec controller as well. This will help you determine if the left-channel and right-channel DAC registers use the entire range of values reserved for 16-bit 2’s complement.