Abstract
The sigma–delta analog-to-digital converter (ADC) has less consumption of circuit power and can achieve higher resolution. In this chapter, a sigma–delta ADC which contains a second-order sigma-delta modulator is presented. The modulator architecture is first designed by using the behavioral simulation of MATLAB, and then the TSMC 0.18 μm single-poly six-metal process. Layout of each analog block has been shown. Simulation results show that, with an input of a −6 dB 1 kHz sine, the delta-sigma ADC can achieve an SNR of 87.2 dB. The core size is 0.6456 mm × 0.3340 mm. With a 16-bit resolution, it is suitable for audio applications.
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Hsieh, CF., Tsai, TH., Chen, CS., Hsieh, YH. (2016). Implementation of a Delta-Sigma Analog-to-Digital Converter. In: Juang, J. (eds) Proceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems (ICITES2014). Lecture Notes in Electrical Engineering, vol 345. Springer, Cham. https://doi.org/10.1007/978-3-319-17314-6_34
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DOI: https://doi.org/10.1007/978-3-319-17314-6_34
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-17313-9
Online ISBN: 978-3-319-17314-6
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