Abstract
Coarse-Grained Reconfigurable Architectures (CGRAs), which provide good trade-offs between performance, hardware/ energy efficiency and flexibility, as well as offer high degree of parallelism, are fast emerging as a competing platform for the high-performance and embedded applications [3]. In this paper, we propose a timing driven approach for generating cycle-accurate high level simulator for CGRA. The simulator is generated from a high-level language describing the CGRA. Experimental results on different architectures and application kernels show that the proposed simulator is \(1.5\times \) to \(4\times \) faster than state-of-the-art RTL simulators.
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Chattopadhyay, A., Chen, X. (2015). A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_24
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DOI: https://doi.org/10.1007/978-3-319-16214-0_24
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