Abstract
This chapter presents the design and measurement results of the fourth and final ultra-low-voltage prototype. Since signal processing applications are the focus of this book, a JPEG encoder is chosen as a representative DSP block to validate the design strategy which has been proposed in this book. The purpose of the JPEG encoder is to demonstrate that the proposed circuit and architectural techniques are generally applicable in any large and complex ultra-low-voltage DSP design. The targets of this prototype remain unchanged: operation at ultra-low supply voltages to enable a high energy-efficiency, operating frequencies in the range of n × 10MHz and high variation-resilience. The design efforts which are made to accomplish these targets are profoundly discussed in this chapter. The JPEG encoder is fabricated in a 40 nm CMOS technology. An overview of the JPEG encoding algorithm is provided, together with the division of the various subblocks which realize this algorithm. The general architectural and gate-level design choices for this ultra-low-voltage prototype is discussed. The chapter also covers the detailed design of the subblocks of the JPEG encoder, with a focus on how the research targets—high energy-efficiency, speed and variation-resilience—are achieved. The measurement results are examined profoundly, whereas an extensive state-of-the-art comparison is provided between all published ultra-low-voltage processors in advanced nanometer CMOS technologies.
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Reynders, N., Dehaene, W. (2015). JPEG Encoder. In: Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-16136-5_6
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DOI: https://doi.org/10.1007/978-3-319-16136-5_6
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