Parallel-Operation-Oriented Optically Reconfigurable Gate Array
Recently, studies exploring acceleration of software operations on a processor have been undertaken aggressively using field programmable gate arrays (FPGAs). However, currently available FPGA architectures present waste occurring with parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous configuration memory parts. Therefore, a parallel-operation-oriented FPGA with a single shared configuration memory for some programmable gate arrays has been proposed. Here, the architecture is applied for optically reconfigurable gate arrays (ORGA). To date, the ORGA architecture has demonstrated that a high-speed dynamic reconfiguration capability can increase the performance of its programmable gate array drastically. Software operations can be accelerated using an ORGA. This paper therefore presents a proposal for combinational architecture of the parallel-operation oriented FPGA architecture and a high-speed reconfiguration ORGA. The architecture is called a parallel-operation-oriented ORGA architecture. For this study, a parallel-operation-oriented ORGA with four programmable gate arrays sharing a common configuration photodiode-array has been designed using 0.18 \(\upmu \)m CMOS process technology. This study clarified the benefits of the parallel-operation-oriented ORGA in comparison with an FPGA having the same gate array structure, produced using the same process technology.
KeywordsParallel Operation Logic Block Comparison Target Switching Matrix Configuration Memory
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