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Parallel-Operation-Oriented Optically Reconfigurable Gate Array

  • Takumi Fujimori
  • Minoru WatanabeEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9017)

Abstract

Recently, studies exploring acceleration of software operations on a processor have been undertaken aggressively using field programmable gate arrays (FPGAs). However, currently available FPGA architectures present waste occurring with parallel operation in terms of configuration memory because the same configuration context corresponding to same-function modules must be programmed onto numerous configuration memory parts. Therefore, a parallel-operation-oriented FPGA with a single shared configuration memory for some programmable gate arrays has been proposed. Here, the architecture is applied for optically reconfigurable gate arrays (ORGA). To date, the ORGA architecture has demonstrated that a high-speed dynamic reconfiguration capability can increase the performance of its programmable gate array drastically. Software operations can be accelerated using an ORGA. This paper therefore presents a proposal for combinational architecture of the parallel-operation oriented FPGA architecture and a high-speed reconfiguration ORGA. The architecture is called a parallel-operation-oriented ORGA architecture. For this study, a parallel-operation-oriented ORGA with four programmable gate arrays sharing a common configuration photodiode-array has been designed using 0.18 \(\upmu \)m CMOS process technology. This study clarified the benefits of the parallel-operation-oriented ORGA in comparison with an FPGA having the same gate array structure, produced using the same process technology.

Keywords

Parallel Operation Logic Block Comparison Target Switching Matrix Configuration Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Archirapatkave, V., Sumilo, H., See, S.C.W., Achalakul, T.: GPGPU acceleration algorithm for medical image reconstruction. In: IEEE International Symposium on Parallel and Distributed Processing with Applications, pp. 41–46 (2011)Google Scholar
  2. 2.
    Unno, M., Inoue, Y., Asar, H.: GPGPU-FDTD method for 2-dimensional electromagnetic field simulation and its estimation. In: IEEE Conference on Electrical Performance of Electronic Packaging and Systems, pp. 239–242 (2009)Google Scholar
  3. 3.
    Lezar, E., Jakobus, U.: GPU-acceleration of the FEKO electromagnetic solution kernel. In: International Conference on Electromagnetics in Advanced Applications, pp. 814–817 (2013)Google Scholar
  4. 4.
    Sano, K., Hatsuda, Y., Yamamoto, S.: Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth. IEEE Transactions on Parallel and Distributed Systems 25(3), 695–705 (2014)CrossRefGoogle Scholar
  5. 5.
    Saidani, T., Atri, M., Said, Y., Tourki, R.: Real time FPGA acceleration for discrete wavelet transform of the 5/3 filter for JPEG 2000. In: International Conference on Sciences of Electronics, Technologies of Information and Telecommunications, pp. 393–399 (2012)Google Scholar
  6. 6.
    Durbano, J.P., Ortiz, F.E.: FPGA-based acceleration of the 3D finite-difference time-domain method. In: IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 156–163 (2004)Google Scholar
  7. 7.
    Sheldon, D., Kumar, R., Lysecky, R., Vahid, F., Tullsen, D.: Application-specific customization of parameterized FPGA soft-core processors. In: IEEE/ACM International Conference on Computer-Aided Design, pp. 261–268 (2006)Google Scholar
  8. 8.
    Zhen, Z., Guilin, T., Dong, Z., Zhiping, H.: Design and realization of the hardware platform based on the Nios soft-core processor. In: International Conference on Electronic Measurement and Instruments, pp. 4–865-4-869 (2007)Google Scholar
  9. 9.
    Hubner, M., Paulsson, K., Becker, J.: Parallel and flexible multiprocessor system-on-chip for adaptive automotive applications based on Xilinx MicroBlaze soft-cores. In: IEEE International Parallel and Distributed Processing Symposium, p. 149a (2005)Google Scholar
  10. 10.
    Watanabe, M.: A parallel-operation-oriented FPGA architecture. In: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, pp. 123–126 (2014)Google Scholar
  11. 11.
    Kubota, S., Watanabe, M.: A four-context programmable optically reconfigurable gate array with a reflective silver-halide holographic memory. IEEE Photonics Journal 3(4), 665–675 (2011)CrossRefGoogle Scholar
  12. 12.
    Nakajima, M., Watanabe, M.: Fast optical reconfiguration of a nine-context DORGA using a speed adjustment control. ACM Transaction on Reconfigurable Technology and Systems 4(2), 1–21 (2011). Article 15CrossRefGoogle Scholar
  13. 13.
    Seto, D., Nakajima, M., Watanabe, M.: Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability. Applied Optics 49(36), 6986–6994 (2010)CrossRefGoogle Scholar
  14. 14.
    Morita, H., Watanabe, M.: Microelectromechanical Configuration of an Optically Reconfigurable Gate Array. IEEE Journal of Quantum Electronics 46(9), 1288–1294 (2010)CrossRefGoogle Scholar
  15. 15.
    Nakajima, M., Watanabe, M.: A four-context optically differential reconfigurable gate array. IEEE/OSA Journal of Lightwave Technology 27(20), 4460–4470 (2009)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Electrical and Electronic EngineeringShizuoka UniversityHamamatsu, ShizuokaJapan

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