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Exploring the Design Space of Signed-Binary Adder Cells

  • David NeuhäuserEmail author
Chapter
  • 717 Downloads
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 343)

Abstract

Arithmetic based on signed-binary number representation is an alternative to carry-save arithmetic. Both offer adders with word-length independent latencies. Comparing both approaches requires optimized adder cells. Small and fast full adder designs have been introduced. A thorough investigation of signed-binary adder cells is still missing. We show that for an example signed-binary encoding scheme the design space consists of 238 different truth tables. Each represents a bit-level signed-binary adder cell. We proposed a new method to enumerate and analyze such a huge design space to gain small area, low power, or low latency signed-binary adder cells and show the limitations of our approach.

Keywords

Signed-digit Signed-binary Adder cell optimization Digital design space exploration 

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Department of Computer Science and MathematicsFriedrich Schiller University JenaJenaGermany

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