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A Synopsis on the State of the Art of NAND Memories

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Charge-Trapping Non-Volatile Memories

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Abstract

NAND memory has become the workhorse nonvolatile memory enabling massive amounts of data to be stored in many electronic devices. There is a high probability that the reader has several devices nearby which contain NAND memory. NAND memory’s combination of simplicity, low cost, high density, low power, and scalability in a solid state device has created a ubiquitous explosion in the NAND market. In 2014, it is estimated that ~6 × 1019 bytes of NAND was shipped (Greg Wong Forward Insights) which is enough to supply a gigabite to every person on the planet (7.2 billion). NAND has crushed less capable memory such as NOR in the market place and is continuing to take market share from hard disk drives pushing them out of the lower density market. As a historical reference a 2013 state of the art 128 Gb 16 nm NAND chip can hold as much data as ~11,000 circa 1986 1.44 MB 90 mm floppy disks which was state of the art at that time (Wikipedia). The impact of NAND on the electronic experience of the consumer has been huge and largely invisible. The accomplishments of the technologists and industry in taking NAND from its invention in 1987 to its dominant position today have been truly amazing. The technology proved to be easily scalable.

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References

  • Aritome S (2013) Study of NAND Flash memory cells. Dissertation. Hiroshima University, Hiroshima

    Google Scholar 

  • Asenov A et al (2001) Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: A 3-D density gradient simulation study. IEEE TRED, New York, NY, p 722

    Google Scholar 

  • Asenov A et al (2003) Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE TRED, New York, NY, p 1254

    Google Scholar 

  • Bae S et al (2009) The 1/f noise and random telegraph noise characteristics in floating gate NAND Flash memories. IEEE TRED, New York, NY, p 1624

    Google Scholar 

  • Belgal H et al (2002) A new reliability model for post cycling charge retention of flash memories. IEEE IRPS, p 7

    Google Scholar 

  • Brewer J et al (2008) Nonvolatile memory with emphasis on Flash. IEEE Press, Piscataway, NJ

    Google Scholar 

  • Brown W et al (1998) Nonvolatile semiconductor memory technology. IEEE Press, Piscataway, NJ

    Google Scholar 

  • Cappelletti P et al (1999) Flash memories. Kluwer, Dordrecht

    Book  Google Scholar 

  • Chang K et al (2012) An advanced embedded flash technology for broad market applications. IEEE ICSICT

    Google Scholar 

  • Compagnoni M et al (2008) Ultimate accuracy for the NAND Flash program algorithm due to the electron injection statistics. IEEE TRED, New York, NY, p 2695

    Google Scholar 

  • Frohman-Bentchkowsky D (1973) Electrically programmable read only memory array. US Patent, 3,744,036

    Google Scholar 

  • Fujiki J et al (2009) Successful suppression of dielectric relaxation inherent to high-K NAND from both architecture and material points of view. IEEE IEDM

    Google Scholar 

  • Ghetti A et al (2005) 3D simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories. Solid State Electron 49(11):1805

    Article  Google Scholar 

  • Goda A et al (2012) Scaling directions for 2-D and 3-D NAND cells. IEEE IEDM

    Google Scholar 

  • Greg Wong Forward-Insights.com

    Google Scholar 

  • Harari E (1978) Electrically erasable non-volatile semiconductor memory. US patent 4,115,914

    Google Scholar 

  • Ho C et al (2008) Improvement of interpoly dielectric characteristics by plasma nitridation and oxidation for future NAND Flash memory. IEEE EDL, New York, NY, p 1199

    Google Scholar 

  • Hou T-H (2007) Design optimization of metal nanocrystal memory, part I: nanocrystal array engineering. IEEE TED 53(12):3095–3102

    Article  Google Scholar 

  • Huff H et al (2005) High dielectric constant materials. Springer, New York, NY, pp 37–38

    Book  Google Scholar 

  • Jung T-S (1996) A 117-mm2 3.3-V only 128-Mb multilevel NAND Flash memory for mass storage. IEEE JSSC 31(11):1575

    Google Scholar 

  • Jung S et al (2008) Modeling of Vth shift in NAND Flash-memory cell device considering crosstalk and short channel effects. IEEE TRED, New York, NY, p 1020

    Google Scholar 

  • Kahng D et al (1967) A Floating Gate and its Application to Memory Device. Bell Syst Tech J 46:1288

    Article  Google Scholar 

  • Kawagoe H et al (1976) Minimum size ROM structure compatible with silicon-gate E/D MOS LSI. IEEE JSSSC. IEEE, New York, NY, p 360

    Google Scholar 

  • Kawamoto. http://www.ieeeghn.org/wiki/index.php/Special:Search?ns0=1&limit=20&offset=0&ns6=1&ns100=1&ns102=1&ns108=1&ns110=1&ns112=1&ns12=1&ns14=1&fulltext=Search&searchx=Search&search=masuoka+NAND+flash&x=78&y=7

  • Kim K (2010) Hot chips memory seminar. Samsung, Seoul

    Google Scholar 

  • Kurata H et al (2007) Random telegraph signal in Flash memory: it’s impact of scaling of multilevel flash memory beyond the 90-nm node. IEEE JSSC, New York, NY, p 1362

    Google Scholar 

  • Lacaze et al (2014) Non-volatile memories ITSE Wiley London UK

    Google Scholar 

  • Lee J (2004) Effects of interface trap generation and annihilation on the data retention characteristics of Flash memory cells. IEEE TDMR, March, p 110

    Google Scholar 

  • Lee J et al (2002) Effects of floating-gate interference on NAND Flash memory cell operation. IEEE EDL, IEEE, New York, NY, p 264

    Google Scholar 

  • Lee CH et al (2006) Charge trapping memory cell of TANOS (si-oxide-SiN-Al2O3-TaN) structure compatible to conventional NAND Flash memory. IEEE NVSMW, p 31

    Google Scholar 

  • Liu C et al (2009) New program disturb phenomenon induced by background data pattern in MLC NAND Flash memory. IEEE IMW

    Google Scholar 

  • Lue H-T et al (2005) BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability. IEDM, 22 Mar 2005

    Google Scholar 

  • Masuoka F et al (1987) New ultra high density EPROM and Flash EEPROM with NAND structure cell. IEDM. IEEE, New York, NY, pp 552–555

    Google Scholar 

  • Micheloni R et al (2010) Inside NAND Flash memories. Springer, New York, NY

    Book  Google Scholar 

  • Mielke N et al (2006) Recovery effects in the distributed cycling of flash memories. IEEE IRPS, p 29

    Google Scholar 

  • Mukerjee S et al (1987) Single transistor electrically programmable memory device and method. US Patent, 4,698,787

    Google Scholar 

  • Mukherjee S et al (1985) A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM, IEDM, p 616

    Google Scholar 

  • Muller R et al (1977) An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate, IEEE JSSC 12(10):507

    Google Scholar 

  • Muralidhar R et al (2003) A 6V embedded 90 nm silicon nanocrystal nonvolatile memory. IEEE, IEDM, pp 601–604

    Google Scholar 

  • Okuyama Y et al (1998) Monte Carlo simulation of stress-induced leakage current by hopping conduction via multi-traps in oxide. IEEE IEDM, p 905

    Google Scholar 

  • Park Y et al (2006) Highly manufacturable 32Gb multi-level NAND Flash memory with .0098 μm2 cell size using TANOS (Si-Oxide-Al203-TaN) cell technology. IEEE IEDM

    Google Scholar 

  • Prall K (2007) Scaling non-volatile memory below 30 nm. IEEE NVSMW, p 5

    Google Scholar 

  • Prall K (2011) New functional materials and emerging device architectures for nonvolatile memories. MRS Proc 1337

    Google Scholar 

  • Prall K et al (2010) 25 nm 64 Gb MLC NAND technology and scaling challenges. IEEE IEDM

    Google Scholar 

  • Raghunathan S et al (2009) Investigation of ballistic current in scaled floating-gate NAND Flash and a solution. IEEE IEDM, p 819

    Google Scholar 

  • Ramaswamy N et al (2013) Engineering a planar NAND cell scalable to 20 nm and beyond. IEEE IMW, p 5

    Google Scholar 

  • Ramkumar K et al (2013) A scalable, low voltage, low cost SONOS Memory technology for embedded NVM applications. IEEE IMW, pp 199–202

    Google Scholar 

  • Reid D et al (2009) Analysis of threshold voltage distribution due to random dopants: a 100000 – sample 3-D simulation study. IEEE TRED, New York, NY, p 2255

    Google Scholar 

  • Richter D (2013) Flash memories: economic principles of performance, cost and reliability optimization. Springer, New York, NY

    Google Scholar 

  • Tanaka H et al (2007) Bit cost scalable technology with punch and plug process for ultra high density flash memory. VLSI Symp Tech Dig, pp 14–15

    Google Scholar 

  • Tega N et al (2006) Anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate Flash memory. IEEE IEDM

    Google Scholar 

  • Torsi A (2011) A program disturb model and channel leakage current study for sub-20 nm NAND Flash cells. IEEE TRED 58:11

    Article  Google Scholar 

  • Wang H et al (2009) A new read-disturb failure mechanism caused by boosting hot-carrier injection effect in MLC NAND Flash. IEEE IMW

    Google Scholar 

  • Waser R (2008) Nanotechnology, vol 3. Wiley, New York, NY

    Google Scholar 

  • Wegener H (1967) The variable threshold transistor, a new electrically alterable non destructive read-only device. IEEE IEDM

    Google Scholar 

  • White M et al (2004) Characterization of scaled SONOS EEPROM memory devices for space and military systems. IEEE NVMT, p 51–59

    Google Scholar 

  • Wikipedia.

    Google Scholar 

  • Yaegashi T et al (2009) 20 nm-node planar MONOS cell technology for multi-level NAND Flash memory. VLSI Tech, pp 190–191

    Google Scholar 

Download references

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Authors and Affiliations

  1. Micron Technology, Inc., Mail Stop 1-715, 8000S. Federal Way, 6, Boise, ID, 83716, USA

    Kirk Prall, Nirmal Ramaswamy & Akira Goda

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  1. Kirk Prall
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  2. Nirmal Ramaswamy
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  3. Akira Goda
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Correspondence to Kirk Prall .

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Editors and Affiliations

  1. National Center for Scientific Research “Demokritos”, Institute of Nanoscience and Nanotechnology, National Center for Scientific Research “Demokritos” , Athens, Greece

    Panagiotis Dimitrakis

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Prall, K., Ramaswamy, N., Goda, A. (2015). A Synopsis on the State of the Art of NAND Memories. In: Dimitrakis, P. (eds) Charge-Trapping Non-Volatile Memories. Springer, Cham. https://doi.org/10.1007/978-3-319-15290-5_2

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