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Motion Estimation for Video Coding pp 65–83Cite as

Efficient Pixel Truncation Algorithm and Architecture

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Part of the book series: Studies in Computational Intelligence ((SCI,volume 590))

Abstract

The goal of this chapter is to introduce a new block matching algorithm, namely the Fast Two Stage Search (F2SS) algorithm and its VLSI architecture for performing low power variable block size Motion Estimation (ME) based on pixel truncation. The chapter starts with a brief discussion on ME methods which adopt the pixel truncation approach.

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Author information

Authors and Affiliations

  1. Department of Electronics and ECE, Indian Institute of Technology Kharagpur, Kharagpur, India

    Indrajit Chakrabarti & Kota Naga Srinivasarao Batta

  2. Department of Electronics and Communication Engineering, National Institute of Technology Sikkim, Ravangla, India

    Sumit Kumar Chatterjee

Authors
  1. Indrajit Chakrabarti
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  2. Kota Naga Srinivasarao Batta
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  3. Sumit Kumar Chatterjee
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Corresponding author

Correspondence to Indrajit Chakrabarti .

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Chakrabarti, I., Batta, K.N.S., Chatterjee, S.K. (2015). Efficient Pixel Truncation Algorithm and Architecture. In: Motion Estimation for Video Coding. Studies in Computational Intelligence, vol 590. Springer, Cham. https://doi.org/10.1007/978-3-319-14376-7_6

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  • DOI: https://doi.org/10.1007/978-3-319-14376-7_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-14375-0

  • Online ISBN: 978-3-319-14376-7

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