A Multi-core Processor
We finally are able to specify a multi-core MIPS machine, build it, and show that it works. Clearly the plan is to take pipelined MIPS machines from Chap. 7 and connect them to the shared memory system from Chap. 8. Before we can do this, however, we have to address a small technical problem: the pipelined machine was obtained by a transformation from a sequential reference implementation, and that machine does not have a compare-and-swap operation. Thus, we have to add an introductory Sect. 9.1, where we augment the sequential instruction set with a compare-and-swap instruction. This turns out to be an instruction with 4 register addresses, where we accommodate the fourth address in the sa field of an R-type instruction. In order to process such instructions in a pipelined fashion we now also need in the sequential reference implementation the ability to read three register operands and to write one register operand in a single hardware cycle. If we would have treated interrupts here, we would have a special purpose register file as in , and we could take the third read operand from there. Here, we simply add a third read port to the general purpose register file using technology from Chap. 4.
In Sect. 9.2 we specify the ISA of multi-core MIPS and give a reference implementation with sequential processors. Like the hardware, ISA and reference implementation can be made completely deterministic, but in order to hide implementation details they are modelled for the user in a nondeterministic way: processors execute instructions one at a time; there is a stepping function s specifying for each time n the processor s(n) executing an instruction at step n. We later derive this function from the implementation, but the user does not know it; thus, programs have to work for any such stepping function. Specifying multi-core ISA turns out to be very easy: we split the sequential MIPS configuration into i) memory and ii) processor (everything else). A multi-core configuration has a single (shared) memory component and multiple processor components. In step n an ordinary sequential MIPS step is executed with processor s(n) and the shared memory.
In the multi-core reference implementation, we hook the sequential reference processors to a memory (which now has to be able to execute compare-and-swap operations). We do not bother to give a hardware construction for this memory; it suffices to use the specification from Sect. 8.2. Note, however, that for this reference implementation of multi-core MIPS we have to generalize the hardware model: we have to partition hardware into portions which are selectively clocked under the control of a stepping function s.
In Sect. 9.3 we “simply” hook pipelined implementations of the sequential MIPS processors into the shared memory system from Sect. 8. The generation of processor inputs to the caches and the consumption of the answers of the memory system are completely straightforward to implement. Unifying the correctness proofs for pipelined processors from Chap. 7 with the lemmas about the shared memory system from Chap. 8 is not terribly difficult any more. It does however require the development of some technical machinery permitting to couple local scheduling functions for the pipelined processors with local instruction numbers of the multi-core reference implementation. Liveness is finally shown using the machinery from Sect. 7.4.