For later use in processors with the MIPS instruction set architecture (ISA), we construct several circuits: as the focus in this book is on correctness and not so much on efficiency of the constructed machine, only the most basic adders and incrementers are constructed in Sect. 5.1. For more advanced constructions see, e.g., . An arithmetic unit (AU) for binary and two’s complement numbers is studied in Sect. 5.2. In our view, understanding the correctness proofs of this section is a must for anyone wishing to understand fixed point arithmetic.
With the help of the AU we construct in Sect. 5.3 an arithmetic logic unit (ALU) for the MIPS ISA in a straightforward way. Differences to  are simply due to differences in the encoding of ALU operations between the MIPS ISA considered here and the DLX ISA considered in .
Also the shift unit considered in Sect. 5.4 is basically from . Shift units are not completely trivial. We recommend to cover this material in the classroom.
As branch instructions in the DLX and the MIPS instruction set architectures are treated in quite different ways, the new Sect. 5.5 with a branch condition evaluation unit had to be included here.