Building on  and , we present at the gate level the construction of a multi-core MIPS machine with “basic” pipelined processors and prove that it works. “Basic” means that the processors only implement the part of the instruction set architecture (ISA) that is visible in user mode; we call it ISA-u. Extending it to the full architecture ISA-sp, that is visible in system programmers mode, we would have to add among other things the following mechanisms: i) local and inter processor interrupts, ii) store buffers, and iii) memory management units (MMUs). We plan to do this as future work. In Sect. 1.1 we present reasons why we think the results might be of interest. In Sect. 1.2 we give a short overview of the book.