Skip to main content

A Very Compact FPGA Implementation of LED and PHOTON

  • Conference paper
  • First Online:
Book cover Progress in Cryptology -- INDOCRYPT 2014 (INDOCRYPT 2014)

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 8885))

Included in the following conference series:

Abstract

LED and PHOTON are new ultra-lightweight cryptographic algorithms aiming at resource-constrained devices. In this article, we describe three different hardware architectures of the LED and PHOTON family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture we propose a round-based implementation while the second is a fully serialized architecture performing operations on a single cell per clock cycle. Then, we propose a novel architecture that is designed with a focus on utilizing commonly available building blocks (SRL16). This new architecture, organized in a complex scheduling of the operations, seems very well suited for recent designs that use serial matrices. We implemented both the lightweight block cipher LED and the lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix-7 (high-end) devices and our new proposed architecture provides very competitive area-throughput trade-offs. In comparison with other recent lightweight block ciphers, the implementation results of LED show a significant improvement of hardware efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash function.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Adas, M.: On The FPGA Based Implementation of SPONGENT (2011). http://ece.gmu.edu/coursewebpages/ECE/ECE646/F11/project/F11_presentations/Marwan.pdf

  2. Aumasson, J.-P., Henzen, L., Meier, W., Naya-Plasencia, M.: Quark: A Lightweight Hash. Journal of Cryptology 26(2), 313–339 (2013)

    Article  MathSciNet  MATH  Google Scholar 

  3. Aysu, A., Gulcan, E., Schaumont, P.: SIMON Says, Break the Area Records for Symmetric Key Block Ciphers on FPGAs. IACR Cryptology ePrint Archive (2014). http://eprint.iacr.org/2014/237

  4. Baldwin, B., Byrne, A., Hamilton, M., Hanley, N., McEvoy, R.P., Pan, W., Marnane, W.P.: FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash. In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, pp. 783–790. IEEE (2009)

    Google Scholar 

  5. Beaulieu, R., Shors, D., Smith, J., Treatman-Clark, S., Weeks, B., Wingers, L.: The SIMON and SPECK Families of Lightweight Block Ciphers. IACR Cryptology ePrint Archive 2013 (2013). http://eprint.iacr.org/2013/404

  6. Bogdanov, A., Knežević, M., Leander, G., Toz, D., Varıcı, K., Verbauwhede, I.: spongent: A Lightweight Hash Function. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 312–325. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  7. Bogdanov, A., Knudsen, L.R., Leander, G., Paar, C., Poschmann, A., Robshaw, M.J.B., Seurin, Y., Vikkelsoe, C.: PRESENT: An Ultra-Lightweight Block Cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450–466. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  8. Bulens, P., Standaert, F.-X., Quisquater, J.-J., Pellegrin, P., Rouvroy, G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) AFRICACRYPT 2008. LNCS, vol. 5023, pp. 16–26. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  9. Canright, D.: A Very Compact S-Box for AES. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 441–455. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  10. Chu, J., Benaissa, M.: Low area memory-free FPGA implementation of the AES algorithm. In: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 623–626. IEEE (2012)

    Google Scholar 

  11. Detrey, J., Gaudry, P., Khalfallah, K.: A Low-Area Yet Performant FPGA Implementation of Shabal. In: Biryukov, A., Gong, G., Stinson, D.R. (eds.) SAC 2010. LNCS, vol. 6544, pp. 99–113. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  12. Eiroa, S., Baturone, I.: FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family. In: FPL, pp. 1–4. IEEE (2013)

    Google Scholar 

  13. Engel, A., Liebig, B., Koch, A.: Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds.) ARC 2011. LNCS, vol. 6578, pp. 261–268. Springer, Heidelberg (2011)

    Google Scholar 

  14. Feldhofer, M., Aigner, M.J., Baier, T., Hutter, M., Plos, T., Wenger, E.: Semi-passive RFID development platform for implementing and attacking security tags. In: ICITST, pp. 1–6. IEEE (2010)

    Google Scholar 

  15. Gong, Z., Nikova, S., Law, Y.W.: KLEIN: A New Family of Lightweight Block Ciphers. In: Juels, A., Paar, C. (eds.) RFIDSec 2011. LNCS, vol. 7055, pp. 1–18. Springer, Heidelberg (2012)

    Google Scholar 

  16. Good, T., Benaissa, M.: AES on FPGA from the Fastest to the Smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 427–440. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  17. Guo, J., Peyrin, T., Poschmann, A.: The PHOTON Family of Lightweight Hash Functions. In: Rogaway, P. (ed.) CRYPTO 2011. LNCS, vol. 6841, pp. 222–239. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  18. Guo, J., Peyrin, T., Poschmann, A., Robshaw, M.: The LED Block Cipher. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 326–341. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  19. Guo, X., Chen, Z., Schaumont, P.: Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors. In: Bereković, M., Dimopoulos, N., Wong, S. (eds.) SAMOS 2008. LNCS, vol. 5114, pp. 106–115. Springer, Heidelberg (2008)

    Google Scholar 

  20. Xilinx Inc. AN 307: Altera Design Flow for Xilinx Users (March 2013). http://www.altera.com/literature/an/an307.pdf

  21. Xilinx Inc., Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs (May 2005). http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

  22. Jungk, B., Reith, S.: On FPGA-based implementations of Grøstl. IACR Cryptology ePrint Archive (2010). http://eprint.iacr.org/2010/260

  23. Kaps, J.-P.: Chai-Tea, Cryptographic Hardware Implementations of xTEA. In: Chowdhury, D.R., Rijmen, V., Das, A. (eds.) INDOCRYPT 2008. LNCS, vol. 5365, pp. 363–375. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  24. Kaps, J.-P., Sunar, B.: Energy Comparison of AES and SHA-1 for Ubiquitous Computing. In: Zhou, X., Sokolsky, O., Yan, L., Jung, E.-S., Shao, Z., Mu, Y., Lee, D.C., Kim, D.Y., Jeong, Y.-S., Xu, C.-Z. (eds.) EUC Workshops 2006. LNCS, vol. 4097, pp. 372–381. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  25. Kaps, J.-P., Yalla, P., Surapathi, K.K., Habib, B., Vadlamudi, S., Gurung, S.: Lightweight Implementations of SHA-3 Candidates on FPGAs. In: The Third SHA-3 Candidate Conference (2012)

    Google Scholar 

  26. Knudsen, L., Leander, G., Poschmann, A., Robshaw, M.J.B.: PRINTcipher: A Block Cipher for IC-Printing. In: Mangard, S., Standaert, F.-X. (eds.) CHES 2010. LNCS, vol. 6225, pp. 16–32. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  27. Macé, F., Standaert, F.-X., Quisquater, J.-J.: FPGA Implementation(s) of a Scalable Encryption Algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(2), 212–216 (2007)

    Article  Google Scholar 

  28. Malka, P.K.: Compact Hardware Implementation of PHOTON Hash Function in FPGA (2011). http://ece.gmu.edu/coursewebpages/ECE/ECE646/F11/project/F11_presentations/Pavan.pdf

  29. Moradi, A., Poschmann, A., Ling, S., Paar, C., Wang, H.: Pushing the Limits: A Very Compact and a Threshold Implementation of AES. In: Paterson, K.G. (ed.) EUROCRYPT 2011. LNCS, vol. 6632, pp. 69–88. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  30. Poschmann, A.Y.: LIGHTWEIGHT CRYPTOGRAPHY: Cryptographic Engineering for a Pervasive World. Phd thesis. Citeseer (2009)

    Google Scholar 

  31. Shibutani, K., Isobe, T., Hiwatari, H., Mitsuda, A., Akishita, T., Shirai, T.: Piccolo: An Ultra-Lightweight Blockcipher. In: Preneel, B., Takagi, T. (eds.) CHES 2011. LNCS, vol. 6917, pp. 342–357. Springer, Heidelberg (2011)

    Chapter  Google Scholar 

  32. Standaert, F.-X., Piret, G., Rouvroy, G., Quisquater, J.-J.: FPGA implementations of the ICEBERG block cipher. Integration, the VLSI Journal 40(1), 20–27 (2007)

    Article  Google Scholar 

  33. Tuan, T., Rahman, A., Das, S., Trimberger, S., Kao, S.: A 90-nm Low-Power FPGA for Battery-Powered Applications. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2), 296–300 (2007)

    Article  Google Scholar 

  34. Yalla, P., Kaps, J.-P.: Lightweight Cryptography for FPGAs. In: International Conference on Reconfigurable Computing and FPGAs, ReConFig 2009, pp. 225–230. IEEE (2009)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to N. Nalla Anandakumar .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer International Publishing Switzerland

About this paper

Cite this paper

Nalla Anandakumar, N., Peyrin, T., Poschmann, A. (2014). A Very Compact FPGA Implementation of LED and PHOTON. In: Meier, W., Mukhopadhyay, D. (eds) Progress in Cryptology -- INDOCRYPT 2014. INDOCRYPT 2014. Lecture Notes in Computer Science(), vol 8885. Springer, Cham. https://doi.org/10.1007/978-3-319-13039-2_18

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-13039-2_18

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-13038-5

  • Online ISBN: 978-3-319-13039-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics