Abstract
The FPGA implementation of CORDIC-like hardware-oriented algorithms, including multidimensional version, with OpenCL kernels are considered. This class of algorithms is also named as discrete linear transformation (DLT). Altera OpenCL SDK is used as a high-level synthesis tool to generate a project for Altera Stratix FPGA family from OpenCL kernels. For the obtained projects clock speed and space requirements are estimated. With this approach, first, the characteristics of the FPGA implementations of multidimensional DLT reflection algorithms are evaluated, in particular, unitary version of Householder-CORDIC reflection. The paper also discusses the possibility of automating the OpenCL kernels generation for the DLT of different dimensions.
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Andreev, A., Doukhnitch, E., Egunov, V., Zharikov, D., Shapovalov, O., Artuh, S. (2014). Evaluation of Hardware Implementations of CORDIC-Like Algorithms in FPGA Using OpenCL Kernels. In: Kravets, A., Shcherbakov, M., Kultsova, M., Iijima, T. (eds) Knowledge-Based Software Engineering. JCKBSE 2014. Communications in Computer and Information Science, vol 466. Springer, Cham. https://doi.org/10.1007/978-3-319-11854-3_20
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DOI: https://doi.org/10.1007/978-3-319-11854-3_20
Publisher Name: Springer, Cham
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