Abstract
This paper presents a design of hardware accelerator for algorithms of rough set theory. A hardware implementation of incremental reduct generation and rule induction is proposed in this paper. Incremental reduct generation algorithm is based on simplified discernibility matrix. The design has been simulated and implemented with Xilinx Artix 7 Field Programmable Gate Array (FPGA) and verified using post synthesis simulation in Xilinx .The hardware accelerator designed is generic and easily reconfigurable due to use of FPGA.The maximum design frequency achieved is 152 MHz. The proposed hardware accelerator is used for the smart grid application. The hardware accelerator extracts important features from the database of the smart grid and generates rules using them. It automates the systems, making it more reliable and less prone to human decision making. It is worth noting that the performance of the hardware accelerator becomes more visible when dealing with larger data sets.
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Tiwari, K.S., Kothari, A.G., Raghavan, K.S.S. (2014). Hardware Accelerator Design Based on Rough Set Philosophy. In: Miao, D., Pedrycz, W., Ślȩzak, D., Peters, G., Hu, Q., Wang, R. (eds) Rough Sets and Knowledge Technology. RSKT 2014. Lecture Notes in Computer Science(), vol 8818. Springer, Cham. https://doi.org/10.1007/978-3-319-11740-9_21
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DOI: https://doi.org/10.1007/978-3-319-11740-9_21
Publisher Name: Springer, Cham
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