Abstract
With the use of ultra-deep submicron technologies, crosstalk has become one of the major causes of failure of signal integrity (SI) in high-speed circuits. Logic faults and time delays in high-speed circuits happen when crosstalk becomes severe, which leads to serious problems during the design verification and test phases in high-speed circuits. In this paper, a vector generation fault test algorithm for crosstalk delay based on the maximum aggressor model and waveform sensitization is proposed for analyzing the four types of crosstalk delay fault in high-speed interconnection circuits; in addition, by improving the traditional FAN algorithm, the proposed algorithm designates a victim line and maximally activates the corresponding aggressive line so as to generate the maximum access delay in a high-speed interconnection circuit induced in a worst-case scenario. In this algorithm, both the gate delay and the line delay are taken into consideration in high-speed interconnection circuits, and two strategies, including static priority and dynamic priority, are examined to achieve a more efficient delay test. The tests were verified in a standard C17 circuit, and the results show that the test vectors for crosstalk delay faults in high-speed circuits can be detected by the proposed algorithm.
Keywords
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Chen WY, Gupta SK, Breuer MA. Test generation for crosstalk-induced delay in integrated circuit. Proceedings of the IEEE International Test Conference; Atlantic; 1999. pp. 191–200.
Krstic A, et al. Delay testing considering crosstalk-induced effects. Proceedings of IEEE International Test Conference; Baltimore; 2001. pp. 558–67.
Min YH, Li ZC, Zhao ZX. Boolean process. Sci China (Ser E). 1996;26(6):542–8.
Zhang Y, Li HW, Gong YZ. The test generation aimed at the delay faults caused by the crosstalk. J Comput Aided Des Graph. 2004;16(10):1448–53.
Yan XL, Liang XL, Shang YL. Test vector generation of the crosstalk delay fault based on MAF model. Comput Eng Appl. 2009;45(19):62–5.
Shang YL. Research on high-speed interconnection crosstalk fault generation. Xi’an: University of Xi’an Electronic Science and Technology; 2009.
Zeng ZD. Digital system test and measurability. Changsha: National Defense Science and Technology University Press; 1992. p. 50–5.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this paper
Cite this paper
Shang, Y., Zhang, P. (2015). ATPG Algorithm for Crosstalk Delay Faults of High-Speed Interconnection Circuits. In: Wong, W. (eds) Proceedings of the 4th International Conference on Computer Engineering and Networks. Lecture Notes in Electrical Engineering, vol 355. Springer, Cham. https://doi.org/10.1007/978-3-319-11104-9_3
Download citation
DOI: https://doi.org/10.1007/978-3-319-11104-9_3
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-11103-2
Online ISBN: 978-3-319-11104-9
eBook Packages: EngineeringEngineering (R0)