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Abstract

One of the main components of a cognitive radio is the radio frequency (RF) wireless transmitter. Similar to the wireless receiver, the main challenge in RF transmitters is wideband, linear operation. In this chapter, various wideband linear transmitter architectures are reviewed, including direct conversion, polar modulator, and direct digital upconversion transmitter architectures. Digital predistortion techniques to correct for analog impairments in the RF transmitter are addressed. The issue of high linearity and power efficiency in output driver amplifiers is discussed.

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References

  1. M. Albulet, RF Power Amplifiers, Atlanta, GA, Noble Publishing, 2001.

    Google Scholar 

  2. Analog Devices. 2.5GSPS Direct Digital Synthesizer with 12-bit DAC, AD9915 Datasheet Rev. B, 2012.

    Google Scholar 

  3. Analog Devices, 3.5GSPS Direct Digital Synthesizer with 12-bit DAC, AD9914 Datasheet Rev. B, 2012.

    Google Scholar 

  4. G. Avitabile and N. Lofu, “EVM Degradation in EDGE Two Point Modulation Scheme due to Quantization Effects,” IEEE Radio and Wireless Conference, 2004, pp. 299–302.

    Google Scholar 

  5. Bastos, J. et. al., “A 12-bit intrinsic accuracy high-speed CMOS DAC,” IEEE J. of Solid-State Circuits, vol. 33, no. 12, Dec 1998, pp. 1959–1969.

    Article  Google Scholar 

  6. E. Bechthum, et. al., “Systematic analysis of the impact of mixing locality on mixing-DAC linearity for multicarrier GSM,” IEEE Int’l Symposium on Circuits and Systems, 2012, pp. 241–244.

    Google Scholar 

  7. A. Behzad, Wireless LAN Radios:System Definition to Transistor Design, Hoboken, New Jersey:John Wiley & Sons, 2008.

    Google Scholar 

  8. Z. Boos et al. “A Fully Digital Multimode Polar Transmitter Employing 17b RF DAC in 3G Mode,” IEEE Int’l Solid-State Circuits Conf (ISSCC), 2011, pp. 376–377.

    Google Scholar 

  9. R. Caverly, CMOS RFIC Design Principles, Norwood, MA, Artech House, 2007.

    Google Scholar 

  10. J. Chen, et. al., “The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator,” IEEE J. of Solid-State Circuits (JSSC), vol. 47, no. 5, May 2012, pp. 1154–1164.

    Article  Google Scholar 

  11. F. E. Churchill, G. W. Ogar, and B. J. Thompson, “The correction of I and Q errors in a coherent processor,” IEEE Trans on Aerospace and Electronic Systems, vol. AES-17, no. 1, pp. 131–137, Jan 1981.

    Article  Google Scholar 

  12. M. Collados, et. al., “A Low-Current Digitally Predistorted 3G-4G Transmitter in 40 nm CMOS,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium 2013, pp. 141–144.

    Google Scholar 

  13. Y. Cong and R. Geiger, “Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays,” IEEE Trans on Circuits and Systems II, vol. 47,no. 7, July 2000, pp. 585–595.

    Article  Google Scholar 

  14. H. Dabag, et. al., “All-Digital Cancellation Technique to Mitigate Receiver Desensitization in Uplink Carrier Aggregation in Cellular Handsets,” IEEE Trans on Microwave Theory and Techniques, vol. 61, no. 12, Part 2, 2013, pp. 4754–4765.

    Article  Google Scholar 

  15. H. Darabi and A. Abidi, “Noise in RF-CMOS mixers:a simple physical model,” IEEE J. of Solid-State Circuits, vol. 35, no. 1, Jan 2000, pp. 15–25.

    Article  Google Scholar 

  16. J. Deveugele, et. al., “A Gradient-Error and Edge-Effect Tolerant Switching Scheme for High-Accuracy DAC,” IEEE Trans on Circuits and Systems I, vol. 51, no. 1, Jan 2004, pp. 191–195.

    Article  Google Scholar 

  17. J. Deveugele, et. al., “A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC,” IEEE Trans on Circuits and Systems I, vol. 50, no. 1, Jan 2004, pp. 191–195.

    Article  Google Scholar 

  18. G. Hueber and R. Staszewski, Multi-Mode/Multi-Band RF Transceivers for Wireless Communications, Hoboken, New Jersey, John Wiley & Sons, 2011.

    Google Scholar 

  19. I. Jung and Y. Kim, “A CMOS low-power digital polar modulator system integration for WCDMA transmitter,” IEEE Trans on Industrial Electronics, vol. 59, no. 2, Feb 2012, pp. 1154–1160.

    Article  Google Scholar 

  20. P. Kennington, R. Wilkinson, K. Parsons, “Noise performance of a Cartesian loop transmitter,” IEEE Trans on Vehicular Technology, vol. 46, no. 2, Feb 1997, pp. 467–476.

    Google Scholar 

  21. K. Krishna, et. al., “Spatial averaging and ordering in matched element arrays,” IEEE Custom Integrated Circuits Conference(CICC), 2002, pp. 453–456.

    Google Scholar 

  22. M. Li, et. al., “Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (invited),” IEEE Workshop on Signal Processing Systems, 2013, pp. 324–329.

    Google Scholar 

  23. F. Luo, Digital Front-End in Wireless Communications and Broadcasting, Cambridge, UK:Cambridge University Press, 2011.

    Book  MATH  Google Scholar 

  24. F. Maloberti, Data Converters, Dorchrecht, Netherlands:Springer, 2007.

    Google Scholar 

  25. Maxim Integrated, 14-Bit, 2.3Gsps Direct RF Synthesis DAC with Selectable Frequency Response, MAX 5879, 2012.

    Google Scholar 

  26. T. Miki, et. al., “An 80-Mhz 8-bit CMOS D/A Converter,” IEEE J. of Solid-State Circuits, vol. SC-21, no. 12, Dec 1986, pp. 983–988.

    Article  Google Scholar 

  27. B. Mohr, et. al., “An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2012, pp. 109–112.

    Google Scholar 

  28. B. Mohr, et. al., “Analysis of digital predistortion architectures for direct digital-to-RF transmitter systems,” IEEE Int’l Midwest Symposium on Circuits and Systems(MWSCAS), 2012, pp. 650–653.

    Google Scholar 

  29. A. Montalvo, “Polar Modulators for Linear Wireless Transmitters,” IEEE Int’l Solid-State Circuits Conference (ISSCC) 2005, T7 tutorial.

    Google Scholar 

  30. Y. Nakamura, et. al., “A 10-b 70-MS/s CMOS D/A Converter,” IEEE J. of Solid-State Circuits, vol. 26, no. 4, Apr 1991, pp. 637–642.

    Article  Google Scholar 

  31. H. Nelson and S. Ferguson, “Digital predistortion techniques for mobile PA test,” High Frequency Electronics, vol. 13, no. 6, June 2014, pp. 32–42.

    Google Scholar 

  32. B. Neurauter, et. al., “GSM 900/DCS 1800 fractional-N modulator with two-point modulation,” Proc of the Microwave Symposium Digest, vol. 1, 2002, pp. 425–428.

    Google Scholar 

  33. M. Norris, “Transmitter Architectures [GSM Handsets],” IEE Colloquium on The Design of Digital Cellular Handsets, 1998, pp. 4/1–4/6.

    Google Scholar 

  34. P. Nuyts, et. al., “A fully digital delay line based GHz range multimode transmitter front-end in 65-nm CMOS,” IEEE J. of Solid-State Circuits, vol. 47, no. 7, July 2012, pp. 1681–1692.

    Article  Google Scholar 

  35. A. Oppenheimer and R. Schafer, Discrete-Time Signal Processing, Upper Saddle River, NJ:Prentice-Hall, 2009.

    Google Scholar 

  36. M. Pelgrom, et. al., “Matching properties of MOS transistors,” IEEE J. of Solid-State Circuits, vol. 24, no. 10, Oct 1989, pp. 1433–1439.

    Article  Google Scholar 

  37. K. Pun, J. da Franca and C. Azeredo-Leme, Circuit Design for Wireless Communications: Improved Techniques for Image Rejection in Wideband Quadrature Receivers, Boston:Kluwer Academic Publishers, 2003.

    Book  Google Scholar 

  38. B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice-Hall, 1998.

    Google Scholar 

  39. P. Roblin, et. al., “Concurrent Linearization,” IEEE Microwave Magazine, vol. 14, no. 7, Nov/Dec 2013, pp. 75–91.

    Article  Google Scholar 

  40. M. Sadeghifar and J. Wikner, “Modeling and analysis of aliasing image spurs problem in digital-RF-converter-based IQ modulators,” IEEE Int’l Symposium on Circuits and Systems (ISCAS), 2013, pp. 578–581.

    Google Scholar 

  41. W. Sander, S. Schell, B. Sander, “Polar Modulator for Multi-mode Cell Phones,” IEEE Custom Integrated Circuits Conf (CICC), 2003, pp. 439–445.

    Google Scholar 

  42. J. Schoeff, “An inherently monotonic 12 bit DAC,” IEEE J. of Solid-State Circuits, vol. SC-14, no. 6, Dec 1979, pp. 940–911.

    Google Scholar 

  43. N. Silva, et. al., “Novel fine tunable multichannel all-digital transmitter,” Proc of the Microwave Symposium Digest, 2013, pp. 1–3.

    Google Scholar 

  44. T. Sowlati, et. al., “Quad-Band GSM/GPRS/EDGE Polar Loop Transmitter,” IEEE J. of Solid-State Circuits, vol. 39, no. 12, Dec 2004, pp. 2179–2189.

    Article  Google Scholar 

  45. J. Staryzk and R. Mohn, “Cost-oriented design of a 14-bit current steering DAC macrocell,” IEEE Int’l Circuits and Systems Conference (ISCAS), vol. 1, 2003, pp. 965–968.

    Google Scholar 

  46. S. Talaeie, et. al., “A 0.18um CMOS fully integrated RFDAC and VGA for WCDMA transmitters,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2008, pp. 157–160.

    Google Scholar 

  47. S. Tang, et. al., “FinFET—a quasi planar double-gate MOSFET,” IEEE Int’l Solid-State Circuits Conference (ISSCC), 2001, pp. 118–119.

    Google Scholar 

  48. Texas Instruments, Quad-Channel, 16-Bit, 1.5GSPS Digital-to-Analog Converter (DAC), DAC34SH84 Datasheet, 2013.

    Google Scholar 

  49. W. Tseng, C. Fan, and J. Wu, “A 12b 1.25GS/s D/A in 90 nm CMOS with > 70 dB SFDR up to 500 MHz,” IEEE Int’l Solid-State Circuits Conf (ISSCC), 2011, pp. 192–193.

    Google Scholar 

  50. P. Vadiyanathan and T. Nguyen, “A TRICK for the design of FIR half-band filters,” IEEE Trans on Circuits and Systems, vol. CAS-34, no. 3, March 1987, pp. 297–300.

    Article  Google Scholar 

  51. R. Vaishnavi and V. Elamaran, “Implementation of CIC filter for DUC/DDC,” Int’l Journal of Engineering and Technology (IJET), vol. 5, no. 1, Feb 2013, pp. 357–365.

    Google Scholar 

  52. G. Van der Plas, et. al., “A 14-bit accuracy intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. of Solid-State Circuits, vol. 34, no. 12, Dec 1999, pp. 1708–1718.

    Article  Google Scholar 

  53. J. Vankka, et. al., “A Multicarrier GMSK Modulator with On-Chip D/A Converter for Base Stations,” IEEE J. of Solid-State Circuits, vol. 37, no. 10, Oct 2002, pp. 1226–1234

    Article  Google Scholar 

  54. J. Volakis, Antenna Engineering Handbook, New York, NY:Mc Graw Hill, 2007.

    Google Scholar 

  55. A. Werquin, A. Frappe, A. Kaiser, “A multi-path multi-rate CMOS polar DPA for wideband multi-standard RF transmitters,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2013, pp. 327–330.

    Google Scholar 

  56. Z. Yu, D. Chen, R. Geiger, “1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs,” IEEE Int’l Conference on Circuits and Systems (ISCAS), vol. 1, 2003, pp. 909–912.

    Google Scholar 

  57. Y. Yu, H. Shi, W. Ni, “An I/Q Channel 12-bit 200MS/s CMOS DAC with Three Stage Decoders for Wireless Communication,” Int’l Conf. on Wireless Communications and Signal Processing, pp. 1–4, 2009.

    Google Scholar 

  58. Z. Zhu, H. Leung and X. Huang, “Challenges in reconfigurable radio transceivers and application of nonlinear signal processing for RF impairment mitigation,” IEEE Circuits and Systems Magazine, pp. 44–63, 2013.

    Google Scholar 

  59. Z. Zhu, et. al., “Challenges in Reconfigurable Radio Transceivers and Application of Nonlinear Signal Processing for RF Impairment Mitigation,” IEEE Circuits and Systems Magazine, vol. 13, no. 1, 2013, pp. 44–65, 2013.

    Article  Google Scholar 

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Correspondence to Amr Fahim .

Summary

Summary

In this chapter, design issues in wideband transmitters have been explored. The requirements of transmitters including EVM, ACPR, and EIRP have been detailed. The simplest transmit architecture, the direct upconverter, has been detailed. The Cartesian loop transmitter has been shown to provide better linearity on the expense of complexity and data bandwidth. Polar modulator architecture, which has gained recent popularity due to its ability to support nonlinear power efficient PAs, has also been detailed.

Special attention has been devoted to direct digital upconverter transmit architectures. This included the digital upconverter filters and upsamplers. It also included an in-depth analysis of DAC design. The concept of DPD as a means to correct for analog impairments has been introduced. Various calibration techniques to correct for nonlinearity as well as image rejection have been given. Finally, various PA topologies have been explored. This included transconductance-based amplifiers, such as class-A, class-B, class-AB, and class-C amplifiers. Switched amplifiers have also been explored, which include class-D, class-E, and class-F amplifiers.

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Fahim, A. (2015). High-Linearity Wideband Transmitter. In: Radio Frequency Integrated Circuit Design for Cognitive Radio Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-11011-0_5

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  • DOI: https://doi.org/10.1007/978-3-319-11011-0_5

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