Abstract
Memory access tracing is one of the widely used methods to evaluate, analyze, and optimize hardware and software designs. We are developing a non-intrusive, scalable, full-address-range memory tracer. The tracer hardware board is compliant with the JEDEC DDR3 DIMM form factor, and fits in a DIMM slot. It is so compact that we can populate up to 16 tracer boards in a 4-CPU server chassis, and record the commands and addresses of all the memory accesses. Each board drives four SSDs to record the memory access addresses without a break until the SSDs are full. For example, we can make a trace of a full SPECjbb 2005 run, which lasts 26 minutes and generates over 11TB trace data. In addition to recording memory accesses, it collects various types of statistical data, such as a large number of segmented read/write statistics and DRAM bank utilization rates, and displays them on the control dashboard in real time.
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Ohba, N., Munetoh, S., Okazaki, A., Katayama, Y. (2014). Non-intrusive Scalable Memory Access Tracer. In: Norman, G., Sanders, W. (eds) Quantitative Evaluation of Systems. QEST 2014. Lecture Notes in Computer Science, vol 8657. Springer, Cham. https://doi.org/10.1007/978-3-319-10696-0_20
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DOI: https://doi.org/10.1007/978-3-319-10696-0_20
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-10695-3
Online ISBN: 978-3-319-10696-0
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