Abstract
In the last 2 years, we have been involved in a project entitled, “a feasible study of a future HPC system for memory-intensive applications.” In this project, we have analyzed some representative applications that need exascale computing around 2020, and clarified design specifications to develop a high-end computing system that will become available around 2018 and be best suited for these applications. This article reports results of a conceptual design and performance estimation of the system obtained through the project.
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References
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Acknowledgements
Many colleagues get involved in this project, and great thanks go to Dr. Y.Kaneda and Dr. K.Watanabe of JAMSTEC (Japan Agency for Marine-Earth Science and Technology) as co-leaders of the application group, Professor M. Yokokawa of Kobe University, Associate Professors H. Takizawa, K. Sano and R. Egawa of Tohoku University, and Dr. K.Itakura of JAMSTEC as sub-leaders of the architecture group, Professor M.Koyanagi of Tohoku University as the leader of the 2.5D/3D device group, and Ms. Y.Hashimoto of NEC as the leader of the NEC application, system and device design groups. This project is supported by Ministry of Education, Culture, Sports, Science and Technology of Japan.
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Kobayashi, H. (2015). Feasibility Study of a Future HPC System for Memory-Intensive Applications: Final Report. In: Resch, M., Bez, W., Focht, E., Kobayashi, H., Patel, N. (eds) Sustained Simulation Performance 2014. Springer, Cham. https://doi.org/10.1007/978-3-319-10626-7_1
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DOI: https://doi.org/10.1007/978-3-319-10626-7_1
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