Abstract
In this chapter, a novel CMOS receiver front-end has been designed,fabricated and verified for short-range optical communications over 1-mm SI-POF channels. First we will present the proposed receiver front-end and we will focus our attention on the main blocks that make it up. Then, we will present the experimental verification of the fabricated prototype. Measurement results will be compared with previously proposed structures in literature. Finally, main conclusions will be drawn.
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References
P. Andreani, A. Bonfanti, L. Romano, C. Samori, Analysis and design of a 1.8-GHz CMOS LC quadrature VCO. IEEE J. Solid-State Circuits 37(12), 1737ā1748 (2002)
M. Atef, R. Swoboda, H. Zimmermann, 1.25Ā Gb/s over 50Ā m Step-index plastic optical fiber using a fully integrated optical receiver with an integrated equalizer. IEEE J. Lightwave Technol. 30(1), 118ā122 (2012)
F. Aznar, S. Celma, B. Calvo, CMOS Receiver Front-Ends for Gigabit Short-Range Optical Communications (Springer, New York, 2013)
F. Aznar, W. Gaberl, H. Zimmermann, A 0.18 um CMOS transimpedance amplifier with 26dB dynamic range at 2.5 Gb/s. Microelectronics J. 42(10), 1136ā1142 (2011)
J.B. Begueret, Y. Deval, C. Scarabello, J.-Y. Le Gall, M. Pignol, An innovative open-loop CDR based on injection-locked oscillator for high-speed data link applications, in Proceedings of 2003 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (2003), pp. 313ā316
Y. Chen, M. Plessis, An integrated 0.35Ā Āµm CMOS optical receiver with clock and data recovery circuit. Microelectron. J. 37(9), 985ā992 (2006)
Y.W.Z. Chen, S.H. Huang, G.W. Wu, C.C. Liu, Y.T. Huang, C.F. Chin, W.H. Chang, Y.Z. Juang, A 3.125Ā Gbps CMOS fully integrated optical receiver with adaptive analog equalizer, in Proceedings of the 2007 IEEE Asian Solid-State Circuits Conference (ASSCC), Nov 2007, pp. 396ā399
E.A. Crain, M.H. Perrot, A 3.125Ā Gb/s limit amplifier in CMOS with 42Ā dB gain and 1Ā Āµs offset compensation. IEEE J. Solid-State Circuits 41(2), 443ā451 (2006)
D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, L. DeVito, A 12.5Ā Mb/s to 2.7Ā Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback. IEEE J. Solid-State Circuits 40(12), 2713ā2725 (2005)
H. Djahanshahi, C.A.T. Salama, Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications. IEEE J. Solid-State Circuits 35(6), 847ā855 (2000)
Y. Dong, K. Martin, A monolithic 3.125Ā Gbps fiber optic receiver front-end for POF applications in 65Ā nm CMOS, in Proceedings of IEEE Custom Integrated Circuits Conference (CICC), Sept 2011, pp. 1ā4
A. Emira, M. AbdelGhany, M. Elsayed, A. Elshurafa, S. Sedky, K. Salama, 50Ā V all PMOS charge pumps using low-voltage capacitors. IEEE Trans. Industr. Electron. 60(10), 4683ā4693 (2013)
C. GarcĆa del Pozo, S. Celma, A. OtĆn, I. Lope, J. UrdangarĆn, 1.8Ā V-3Ā GHz CMOS limiting amplifier with efficient frequency compensation. Microelectron. Reliab. 50(12), 2084ā2089 (2010)
F. Gerfers, G.W. den Besten, P.V. Petkov, J.E. Conder, A.J. Koellmann, A 0.2ā2Ā Gb/s 6x OSR receiver using a digitally self- adaptive equalizer. IEEE J. Solid-State Circuits 43(6), 1436ā1448 (2008)
C. Gimeno, C. Aldea, S. Celma, F. Aznar, C. SĆ”nchez-Azqueta, A CMOS continuous-time equalizer for short-reach optical communications, in Proceedings of 20th European Conference on Circuit Theory and Design (ECCTD 2011), Aug 2011, pp. 153ā156
C. Gimeno, C. Aldea, S. Celma, F. Aznar, A cost-effective 1.25-Gb/s CMOS receiver for 50-m large-core SI-POF links. IEEE Photonics Technol. Lett. 24(6), 485ā487 (2012)
C. Gimeno, C. Aldea, S. Celma, F. Aznar, Low-voltage low-power CMOS receiver front-end for gigabit short-reach optical communications. Int. J. Circuit Theory Appl. 41(11), 1175ā1187 (2013)
M. Hsieh, G.E. Sobelman, Architectures for multi-gigabit wire-linked clock and data recovery. IEEE Circuits Syst. Mag. 4(4), 45ā57 (2008)
H. Huang, J. Chien, L. Lu, A 10Ā Gb/s inductorless CMOS limiting amplifier with third-order interleaving active feedback. IEEE J. Solid-State Circuits 42(5), 1111ā1120 (2007)
IEC 60825-1 International Standard. Edition 2.0 (2007)
M. Ierssel, A. Sheikholeslami, H. Tamura, W.W. Walker, A 3.2Ā Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance. IEEE J. Solid-State Circuits 42(10), 2224ā2234 (2007)
L. Jianhua, T. Lei, C. Haitao, X. Tingting, C. Zhiheng, W. Zhigong, Design techniques of CMOS SCL circuits for Gb/s applications, in Proceedings of 4th International Conference on ASIC 2001, Oct 2001, pp. 559ā562
M. Kamiya, H. Ikeda, S. Shinohara, Analog data transmission through plastic optical fiber in robot with compensation of errors caused by optical fiber bending loss. IEEE Trans. Industr. Electron. 48(5), 1034ā1037 (2001)
M. Kamiya, H. Ikeda, S. Shinohara, Wavelength-division-multiplexed analog transmission through plastic optical fiber for use in factory communications. IEEE Trans. Industr. Electron. 49(2), 507ā510 (2002)
T. Kok-Siang, M.-S. Sulaiman, M. Reaz, C. Hean-Teik, M. Sachdev, A 3.2Ā Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance. Analog Integr. Circ. Sig. Process 51(2), 101ā109 (2007)
A.M.J. Koonen, A. Pizzinat, E. Ortego Martinez, J. Faller, B. Lannoo, H.P.A. van den Boom, C.M. Okonkwo, Y. Shi, E. Tangdiongga, P. Guignard, B. Charbonnier, A look into the future of in-building networks: roadmapping the fiber invasion, in Proceedings of the 20th International Conference on Plastic Optical Fibers (POF2011), Sep 2011, pp. 41ā46
C. Liao, S. Liu, A 40Ā Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery. IEEE J. Solid-State Circuits 43(11), 2492ā2502 (2008)
P. Muller, Y. Leblebici, Limiting amplifiers for next-generation multi-channel optical I/O interfaces in SoCs, in Proceedings of IEEE International SOC Conference, Sep 2005, pp. 193ā196
V. Peluso, P. Vancorenland, A.M. Marques, M.S.J. Steyaert, W. Sansen, A 900-mV low-power ĪĪ£ A/D converter with 77-dB dynamic range. IEEE J. Solid-State Circuits 33(12), 1887ā1897 (1998)
S. Radovanovic, A.J. Annema, B. Nauta, Physical and electrical bandwidths of integrated photodiodes in standard CMOS technology, in IEEE Conference on Electron Devices and Solid-State Circuits, Dec 2003, pp. 95ā98
B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits (Wiley, New York, 1996)
B. Razavi, Prospects of CMOS technology for high-speed optical communication circuits. IEEE J. Solid-State Circuits 37(9), 1135ā1145 (2002)
B. Razavi, Challenges in the design of high-speed clock and data recovery circuits. IEEE Commun. Mag. 40(8), 94ā101 (2002)
B. Razavi, Design of Integrated Circuits for Optical Communications (McGraw-Hill, 2003)
D. Rennie, M. Sachdev, Comparative robustness of CML phase detectors for clock and data recovery circuits, in International Symposium on Quality Electronic Design (ISQED), Mar 2007, pp. 305ā310
D. Rennie, M. Sachdev, A 5-Gb/s CDR circuit with automatically calibrated linear phase detector. IEEE Trans. Circuits Syst. I Regul. Pap. 55(3), 796ā803 (2008)
J.J.F. Rijns, 54Ā MHz switched-capacitor video channel equaliser. Electron. Lett. 29(25), 2181ā2182 (1993)
L. Rodoni, G. von BĆ¼ren, A. Huber, M. Schmarz, H. JƤckel, A 5.75 to 44Ā Gb/s quarter rate CDR with data rate selection in 90Ā nm bulk CMOS. IEEE J. Solid-State Circuits 44(7), 1927ā1941 (2009)
E. SƤckinger, Broadband circuits for optical fiber communication (Wiley Interscience, New Jersey, 2005)
E. SƤckinger, The transimpedance limit. IEEE Trans. Circuits Syst. I Regul. Pap. 57(8), 1848ā1856 (2010)
C. SĆ”nchez-Azqueta, S. Celma, A phase detection scheme for clock and data recovery applications, in European Conference on Circuit Theory and Design (ECCTD 2011), Aug 2011, pp. 129ā132
C. SĆ”nchez-Azqueta, S. Celma, F. Aznar, A 0.18Ā Āµm CMOS ring VCO for clock and data recovery applications, Microelectron. Reliab. 51(12), 2351ā2356 (2011)
C. SƔnchez-Azqueta, S. Celma, Multi-gigabit clock and data recovery architecture in CMOS technology. PhD Thesis, Universidad de Zaragoza (2012)
C. SĆ”nchez-Azqueta, C. Gimeno, E. Guerrero, C. Aldea, S. Celma, A low-power CMOS receiver for 1.25-Gb/s over 1-mm SI-POF links. IEEE Trans. Industr. Electron. 61(8), 4246ā4254 (2014)
J. Savoj, B. Razavi, A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE J. Solid-State Circuits 36(5), 761ā768 (2001)
C. Scarabello, J.-B. Begueret, Y. Deval, D. Deschans, P. Fouillat, M. Pignol, J.-Y. Le Gall, A novel 1Ā Gbps clock and data recovery architecture using synchronous oscillator in CMOS VLSI technology, in Proceedings of the 28th European Solid-State Circuits Conference (ESSCIRC 2002), Sept 2002, pp. 779ā782
J. Sundermeyer, C. Zerna, J. Tan, Integrated analogue adaptive equalizer for gigabit transmission over standard step index plastic optical fibre (SI-POF), in Proceedings of LEOS Annual Meeting Conference, Oct 2009, pp. 195ā196
R. Tao, The design of wide bandwidth front-end amplifiers for high speed optical interconnects. Elektrotechnik (Shaker Verlag, 2006)
F. Tavernier, M. Steyaert, A high-speed POF receiver with 1Ā mm integrated photodiode in 180Ā nm CMOS, in 36th European Conference and Exhibition on Optical Communication, Sept 2010, pp. 1ā3
H. Wu, C. Yang, A 3.125-GHz limiting amplifier for optical receiver system, in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), Dec 2006, pp. 2010ā2013
H. Xi, Q. Jin, X. Ruan, Feed-forward scheme considering bandwidth limitation of operational amplifiers for envelope tracking power supply using series-connected composite configuration. IEEE Trans. Industr. Electron. 60(9), 3915ā3926 (2013)
S. Yan, Y. Chen, T. Wang, H. Wang, A 40-Gb/s quarter rate CDR with 1:4 demultiplexer in 90-nm CMOS technology, in 12th IEEE International Conference on Communication Technology (ICCT), Nov 2010, pp. 673ā676
R. Zhang, G.S.L. Rue, Fast acquisition clock and data recovery circuit with low jitter. IEEE J. Solid-State Circuits 41(5), 1016ā1024 (2006)
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Gimeno Gasca, C., Celma Pueyo, S., Aldea Chagoyen, C. (2015). Receiver Front-End for 1.25-Gb/s SI-POF. In: CMOS Continuous-Time Adaptive Equalizers for High-Speed Serial Links. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-10563-5_5
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DOI: https://doi.org/10.1007/978-3-319-10563-5_5
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