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Physically Unclonable Function: Principle, Design and Characterization of the Loop PUF

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Trusted Computing for Embedded Systems

Abstract

This chapter presents a novel Physically Unclonable Function PUF called “Loop PUF” (LPUF) which has been studied specifically to be easy to design, lightweight and reliable. The LPUF principle is based on a loop of N controllable delay lines forming a unique ring oscillator. It offers a huge set of challenges as the identity extraction is performed by N measurements, whereas the extraction is made differentially for the other delay-based PUF. This property allows the designer to forge stronger challenge-response protocols or to generate more reliable internal keys. The LPUF concept has been designed and evaluated in ASIC 65 nm technology and in FPGA Virtex-5. The evaluation results show good properties of randomness and uniqueness. As the LPUF output is in integer format and can use numerous challenges, it provides a good base to enhance the steadiness and build reliable authentication protocols. This chapter presents an example of authentication primitive which is very steady in a large range of environmental conditions.

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References

  1. Cherif, Z., Danger, J.L., Bossuet, L.: Performance evaluation of physically unclonable function by delay statistics. In: NEWCAS, Bordeaux (2011)

    Google Scholar 

  2. Gassend, B., Clarke, D.E., van Dijk, M., Devadas, S.: Silicon physical random functions. In: ACM Conference on Computer and Communications Security, Washington, DC, USA, pp. 148–160 (2002)

    Google Scholar 

  3. Guajardo, J., Kumar, S.S., Schrijen, G.J., Tuyls, P.: FPGA intrinsic PUFs and their use for IP protection. In: CHES, Vienna. Lecture Notes in Computer Science, pp. 63–80. Springer (2007)

    Google Scholar 

  4. Hori, Y., Yoshida, T., Katashita, T., Satoh, A.: Quantitative and statistical performance evaluation of arbiter physical unclonable functions on FPGAs. In: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp. 298–303 (2010). doi:http://doi.ieeecomputersociety.org/10.1109/ReConFig.2010.24

  5. Jouini, Z.C., Danger, J.L., Guilley, S., Bossuet, L.: An easy to design PUF based on a single oscillator: the loop PUF. In: DSD’12, Izmir, Turkey (2012)

    Google Scholar 

  6. Kumar, S.S., Guajardo, J., Maes, R., Schrijen, G.J., Tuyls, P.: The butterfly PUF: protecting IP on every FPGA. In: Tehranipoor, M., Plusquellic, J. (eds.) HOST, pp. 67–70. IEEE Computer Society (2008)

    Google Scholar 

  7. Majzoobi, M., Koushanfar, F., Potkonjak, M.: Lightweight secure PUFs. In: Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, ICCAD’08, San Jose, USA, pp. 670–673. IEEE, Piscataway (2008). http://portal.acm.org/citation.cfm?id=1509456.1509603

  8. Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. In: Proceedings of the 17th ACM Conference on Computer and Communications Security, CCS’10, Chicago, USA, pp. 237–249. ACM, New York (2010). doi:http://doi.acm.org/10.1145/1866307.1866335

  9. Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: DAC, San Diego, USA, pp. 9–14 (2007)

    Google Scholar 

  10. Xilinx: Virtex-5 libraries guide for hdl designs. http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/virtex5_hdl.pdf

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Correspondence to Jean-Luc Danger .

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Cherif, Z., Danger, JL., Lozac’h, F., Nguyen, P. (2015). Physically Unclonable Function: Principle, Design and Characterization of the Loop PUF. In: Candaele, B., Soudris, D., Anagnostopoulos, I. (eds) Trusted Computing for Embedded Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-09420-5_6

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  • DOI: https://doi.org/10.1007/978-3-319-09420-5_6

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