Skip to main content
SpringerLink
Log in

Automated Debugging for Logic Bugs

  • Chapter
  • First Online:
Debug Automation from Pre-Silicon to Post-Silicon

  • 774 Accesses

Abstract

Automated debugging approaches are necessary to speed up the design process as size and complexity of VLSI designs increase. Among these approaches, debugging based on SAT [SVAV05] has been shown as a robust and efficient approach. The purpose of SAT-based debugging is to identify the potential sources of an observed error by using the available counterexamples utilizing the practical efficiency of SAT-based reasoning engines for NP-complete problems. Each potential source of the error is returned as a fault candidate which is a set of components of the circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. A reconfigurable design-for-debug infrastructure for SoCs. In Proceedings of the Design Automation Conference, pages 7–12, 2006.

    Google Scholar 

  2. Aseem Agarwal, David Blaauw, and Vladimir Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In Proceedings of the International Conference on Computer-Aided Design, pages 900–907, 2003.

    Google Scholar 

  3. Robert C Aitken. Modeling the unmodelable: Algorithmic fault diagnosis. IEEE Design & Test of Computers, 14(3):98–103, 1997.

    Google Scholar 

  4. Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, and Zainalabedin Navabi. Online NoC switch fault detection and diagnosis using a high level fault mode. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 21–30, 2007.

    Google Scholar 

  5. Ehab Anis and Nicola Nicolici. Low cost debug architecture using lossy compression for silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 1–6, 2007.

    Google Scholar 

  6. Massimo Alioto, Gaetano Palumbo, and Melita Pennisi. Understanding the effect of process variations on the delay of static and domino logic. IEEE Transactions on VLSI Systems, 18(5):697–710, 2010.

    Article  Google Scholar 

  7. Moayad Fahim Ali, Sean Safarpour, Andreas Veneris, Magdy S Abadir, and Rolf Drechsler. Post-verification debugging of hierarchical designs. In Proceedings of the International Conference on Computer-Aided Design, pages 871–876, 2005.

    Google Scholar 

  8. Franc Brglez, David Bryan, and Krzysztof Kozminski. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1929–1934, 1989.

    Google Scholar 

  9. David Blaauw, Kaviraj Chopra, Ashish Srivastava, and Louis Scheffer. Statistical timing analysis: From basic principles to state of the art. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(4):589–607, 2008.

    Article  Google Scholar 

  10. Armin Biere, Marijn J. H. Heule, Hans van Maaren, and Toby Walsh, editors. Handbook of Satisfiability, volume 185 of Frontiers in Artificial Intelligence and Applications. IOS Press, February 2009.

    Google Scholar 

  11. Pouria Bastani, Kip Killpack, Li-C. Wang, and Eli Chiprout. Speedpath prediction based on learning from a small set of examples. In Proceedings of the Design Automation Conference, pages 217–222, 2008.

    Google Scholar 

  12. Luca Benini and Giovanni De Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70–78, 2002.

    Article  Google Scholar 

  13. Franc Brglez, Phillip Pownall, and Robert Hum. Accelerated ATPG and fault grading via testability analysis. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 695–698, 1985.

    Google Scholar 

  14. Melvin A. Breuer. Hardware that produces bounded rather than exact results. In Proceedings of the Design Automation Conference, pages 871–876, 2010.

    Google Scholar 

  15. Franc Brglez. A fast fault grader: Analysis and applications. In Proceedings of the International Test Conference, pages 785–794, 1985.

    Google Scholar 

  16. Caroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, and Marcos Herve. Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In IEEE International On-Line Testing Symposium, pages 61–66, 2009.

    Google Scholar 

  17. John D Carpinelli. Computer systems organization & architecture. Addison-Wesley Boston, San Francisco, New York, 2001.

    Google Scholar 

  18. Yung-Chang Chang, Ching-Te Chiu, Shih-Yin Lin, and Chung-Kai Liu. On the design and analysis of fault tolerant NoC architecture using spare routers. In Proceedings of the ASP Design Automation Conference, pages 431–436, 2011.

    Google Scholar 

  19. Pi-Yu Chung and Ibrahim N. Hajj. Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Transactions on VLSI Systems, 5(2):233–237, 1997.

    Article  Google Scholar 

  20. Edmund M. Clarke, Daniel Kroening, and Karen Yorav. Specifying and verifying systems with multiple clocks. In International Conference on Computer Design, pages 48–55, 2003.

    Google Scholar 

  21. Kypros Constantinides, Onur Mutlu, and Todd M. Austin. Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. In International Symposium on Microarchitecture, pages 282–293, 2008.

    Google Scholar 

  22. Kypros Constantinides, Onur Mutlu, Todd M. Austin, and Valeria Bertacco. A flexible software-based framework for online detection of hardware defects. IEEE Transactions Computers, 58(8):1063–1079, 2009.

    Article  MathSciNet  Google Scholar 

  23. Kai-Hui Chang, Igor L. Markov, and Valeria Bertacco. Automating post-silicon debugging and repair. In Proceedings of the International Conference on Computer-Aided Design, pages 91–98, 2007.

    Google Scholar 

  24. Kai-Hui Chang, Igor L Markov, and Valeria Bertacco. Fixing design errors with counterexamples and resynthesis. In Proceedings of the ASP Design Automation Conference, pages 944–949, 2007.

    Google Scholar 

  25. Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, and Srimat T. Chakradhar. Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. In Proceedings of the Design Automation Conference, pages 555–560, 2010.

    Google Scholar 

  26. Concept Engineering GmbH, http://www.concept.de/RTLvision.html [accessed: 2014-05-20]. RTLvision PRO, 2014.

  27. Srimat T. Chakradhar and Anand Raghunathan. Best-effort computing: re-thinking parallel software and hardware. In Proceedings of the Design Automation Conference, pages 865–870, 2010.

    Google Scholar 

  28. Yibin Chen, Sean Safarpour, Joao Marques-Silva, and Andreas Veneris. Automated design debugging with maximum satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(11):1804–1817, 2010.

    Article  Google Scholar 

  29. S. Davidson. ITC99 Benchmark. http://www.cerc.utexas.edu/itc99-benchmarks/bench.html [accessed: 2014-05-20], 1999.

  30. Mehdi Dehbashi and Goerschwin Fey. Automated debugging from pre-silicon to post-silicon. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 324–329, 2012.

    Google Scholar 

  31. Mehdi Dehbashi and Goerschwin Fey. Debug automation for logic circuits under timing variations. IEEE Design & Test of Computers, 30(6):60–69, 2013.

    Article  Google Scholar 

  32. Mehdi Dehbashi and Goerschwin Fey. Efficient automated speedpath debugging. In IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pages 48–53, 2013.

    Google Scholar 

  33. Mehdi Dehbashi and Goerschwin Fey. Debug automation for synchronization bugs at RTL. In Proceedings of the International Conference on VLSI Design, 2014.

    Google Scholar 

  34. Mehdi Dehbashi and Goerschwin Fey. Transaction-based online debug for NoC-based multiprocessor SoCs. In Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP), 2014.

    Google Scholar 

  35. Mehdi Dehbashi, Goerschwin Fey, Kaushik Roy, and Anand Raghunathan. On modeling and evaluation of logic circuits under timing variations. In EUROMICRO Symp. on Digital System Design, pages 431–436, 2012.

    Google Scholar 

  36. Johan de Kleer and James Kurien. Fundamentals of model-based diagnosis. In IFAC Symposium on Fault Detection, Supervision, and Safety of Technical Processes, pages 25–36, 2003.

    Google Scholar 

  37. Flavio M. de Paula, Amir Nahir, Ziv Nevo, Avigal Orni, and Alan J. Hu. TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead. In Proceedings of the Design Automation Conference, pages 411–416, 2011.

    Google Scholar 

  38. Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. In EUROMICRO Symp. on Digital System Design, pages 479–486, 2011.

    Google Scholar 

  39. Mehdi Dehbashi, André Sülflow, and Goerschwin Fey. Automated design debugging in a testbench-based verification environment. Microprocessors and Microsystems, 37(2):206–217, 2013.

    Article  Google Scholar 

  40. Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, and Michael Velten. Requirements and concepts for transaction level assertions. In International Conference on Computer Design, 2006.

    Google Scholar 

  41. Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, and Trevor N. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In International Symposium on Microarchitecture, pages 7–18, 2003.

    Google Scholar 

  42. Niklas Eén and Niklas Sörensson. An extensible SAT solver. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing, volume 2919 of Lecture Notes in Computer Science, pages 502–518, 2004.

    Google Scholar 

  43. M Fahim Ali, Andreas Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, and Magdy Abadir. Debugging sequential circuits using Boolean satisfiability. In Proceedings of the International Conference on Computer-Aided Design, pages 204–209, 2004.

    Google Scholar 

  44. Goerschwin Fey and Rolf Drechsler. Efficient hierarchical system debugging for property checking. In In IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pages 41–46, 2005.

    Google Scholar 

  45. Goerschwin Fey, Stefan Staber, Roderick Bloem, and Rolf Drechsler. Automatic fault localization for property checking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6):1138–1149, 2008.

    Article  Google Scholar 

  46. Gerhard Friedrich, Markus Stumptner, and Franz Wotawa. Model-based diagnosis of hardware designs. Artificial Intelligence, 111(1–2):3–39, 1999.

    Article  MATH  MathSciNet  Google Scholar 

  47. Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based debugging of system-on-chips with patterns. In International Conference on Computer Design, pages 186–192, 2009.

    Google Scholar 

  48. Amir Masoud Gharehbaghi and Masahiro Fujita. Transaction-based post-silicon debug of many-core system-on-chips. In Proceedings of the International Symposium on Quality Electronic Design, pages 702–708, 2012.

    Google Scholar 

  49. Malay K. Ganai and Aarti Gupta. Efficient BMC for multi-clock systems with clocked specifications. In Proceedings of the ASP Design Automation Conference, pages 310–315, 2007.

    Google Scholar 

  50. Alex Groce and Daniel Kroening. Making the most of BMC counterexamples. Electronic Notes in Theoretical Computer Science, 119(2):67–81, 2005.

    Article  Google Scholar 

  51. Kunal P. Ganeshpure and Sandip Kundu. On ATPG for multiple aggressor crosstalk faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5):774–787, 2010.

    Article  Google Scholar 

  52. Torsten Grüning, Udo Mahlstedt, and Hartmut Koopmeiners. DIATEST: A fast diagnostic test pattern generator for combinational circuits. In Proceedings of the International Conference on Computer-Aided Design, pages 194–197, 1991.

    Google Scholar 

  53. Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, and Kaushik Roy. IMPACT: imprecise adders for low-power approximate computing. In International Symposium on Low Power Electronics and Design, pages 409–414, 2011.

    Google Scholar 

  54. Amirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, and Valeria Bertacco. Comprehensive online defect diagnosis in on-chip networks. In Proceedings of the VLSI Test Symposium, pages 44–49, 2012.

    Google Scholar 

  55. Orna Grumberg, Assaf Schuster, and Avi Yadgar. 3-valued circuit SAT for STE with automatic refinement. In Automated Technology for Verification and Analysis, pages 457–473, 2007.

    Google Scholar 

  56. Aarti Gupta. SAT-based scalable formal verification solutions. Springer, 2007.

    Google Scholar 

  57. Kees Goossens, Bart Vermeulen, Remco Van Steeden, and Martijn Bennebroek. Transaction-based communication-centric debug. In International Symposium on Networks-on-Chips, pages 95–106, 2007.

    Google Scholar 

  58. Mingzhi Gao, Zuochang Ye, Yao Peng, Yan Wang, and Zhiping Yu. A comprehensive model for gate delay under process variation and different driving and loading conditions. In Proceedings of the International Symposium on Quality Electronic Design, pages 406–412, 2010.

    Google Scholar 

  59. John P. Hayes. Fault modeling. IEEE Design & Test of Computers, pages 37–44, 1985.

    Google Scholar 

  60. Andrew B. T. Hopkins and Klaus D. McDonald-Maier. Debug support for complex systems on-chip: a review. IEE Proceedings on Computers and Digital Techniques, 153(4):197 – 207, 2006.

    Google Scholar 

  61. IEEE. IEEE Std 1850–2005 – IEEE Standard for Property Specification Language (PSL). The IEEE, 2005.

    Google Scholar 

  62. L. Jain. NIRGAM: A Simulator for NoC Interconnect Routing and Application Modeling – Version 1.1, 2007. http://nirgam.ecs.soton.ac.uk/ [accessed: 2014-05-20].

  63. Tai-Ying Jiang, C-NJ Liu, and Jing-Yang Jou. Accurate rank ordering of error candidates for efficient HDL design debugging. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):272–284, 2009.

    Google Scholar 

  64. Kip Killpack, Chandramouli V. Kashyap, and Eli Chiprout. Silicon speedpath measurement and feedback into EDA flows. In Proceedings of the Design Automation Conference, pages 390–395, 2007.

    Google Scholar 

  65. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. Slack redistribution for graceful degradation under voltage overscaling. In Proceedings of the ASP Design Automation Conference, pages 825–831, 2010.

    Google Scholar 

  66. JA Knottnerus and JW Muris. Assessment of the accuracy of diagnostic tests: the cross-sectional study. Journal of Clinical Epidemiology, 56(11):1118–1128, 2003.

    Article  Google Scholar 

  67. Ho Fai Ko and Nicola Nicolici. Automated trace signals identification and state restoration for improving observability in post-silicon validation. In Proceedings of Design, Automation and Test in Europe, pages 1298–1303, 2008.

    Google Scholar 

  68. Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, and Pouria Bastani. Case study on speed failure causes in a microprocessor. IEEE Design & Test of Computers, 25(3):224–230, 2008.

    Article  Google Scholar 

  69. Tracy Larrabee. Test pattern generation using boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(1): 4–15, 1992.

    Article  Google Scholar 

  70. Damjan Lampret and Julius Baxter. OpenRISC 1200 IP Core Specification (Preliminary Draft), 2014. http://www.openrisc.net [accessed: 2014-05-20].

  71. Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, and Subhasish Mitra. ERSA: Error resilient system architecture for probabilistic applications. In Proceedings of Design, Automation and Test in Europe, pages 1560–1565, 2010.

    Google Scholar 

  72. Min Li, Azadeh Davoodi, and Lin Xie. Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. In Proceedings of Design, Automation and Test in Europe, pages 1591–1596, 2012.

    Google Scholar 

  73. Avinash Lingamneni, Christian Enz, Jean-Luc Nagel, Krishna Palem, and Christian Piguet. Energy parsimonious circuit design through probabilistic pruning. In Proceedings of Design, Automation and Test in Europe, pages 764–769, 2011.

    Google Scholar 

  74. Hoang M. Le, Daniel Große, and Rolf Drechsler. Automatic TLM fault localization for SystemC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(8):1249–1262, 2012.

    Article  Google Scholar 

  75. Yung-Chieh Lin, Feng Lu, and Kwang-Ting Cheng. Multiple-fault diagnosis based on adaptive diagnostic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(5):932–942, 2007.

    Article  Google Scholar 

  76. Yeonbok Lee, Takeshi Matsumoto, and Masahiro Fujita. On-chip dynamic signal sequence slicing for efficient post-silicon debugging. In Proceedings of the ASP Design Automation Conference, pages 719–724, 2011.

    Google Scholar 

  77. Wing-Ning Li, Sudhakar M Reddy, and Sartaj K Sahni. On path selection in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(1):56–63, 1989.

    Google Scholar 

  78. Jean Davies Lesser and John J. Shedletsky. An experimental delay test generator for LSI logic. IEEE Transactions on Computers, 100(3):235–248, 1980.

    Google Scholar 

  79. Jiang Brandon Liu and Andreas Veneris. Incremental fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2): 240–251, 2005.

    Google Scholar 

  80. Leonard Lee, Li-C. Wang, Praveen Parvathala, and T. M. Mak. On silicon-based speed path identification. In Proceedings of the VLSI Test Symposium, pages 35–41, 2005.

    Google Scholar 

  81. Xiao Liu and Qiang Xu. On signal tracing for debugging speedpath-related electrical errors in post-silicon validation. In Proceedings of the IEEE Asian Test Symposium, pages 243–248, 2010.

    Google Scholar 

  82. Wojciech Maly. Realistic fault modeling for VLSI testing. In Proceedings of the Design Automation Conference, pages 173–180. ACM, 1987.

    Google Scholar 

  83. Patrick C McGeer and Robert K Brayton. Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications. Kluwer Academic Publishers, 1991.

    Google Scholar 

  84. K. McElvain. IWLS’93 Benchmark Set: Version 4.0. http://www.cbl.ncsu.edu/benchmarks/LGSynth93 [accessed: 2014-05-20], 1993.

  85. Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, and Kaushik Roy. Design of voltage-scalable meta-functions for approximate computing. In Proceedings of Design, Automation and Test in Europe, pages 950–955, 2011.

    Google Scholar 

  86. Yashwant K Malaiya, AP Jayasumana, and R Rajsuman. A detailed examination of bridging faults. In International Conference on Computer Design, pages 78–81, 1986.

    Google Scholar 

  87. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, and Janusz Rajski. Timing-aware multiple-delay-fault diagnosis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(2):245–258, 2009.

    Article  Google Scholar 

  88. Joao Marques-Silva. Search algorithms for satisfiability problems in combinational switching circuits. PhD thesis, University of Michigan, 1995.

    Google Scholar 

  89. Wolfgang Mayer and Markus Stumptner. Model-based debugging–state of the art and future challenges. Electronic Notes in Theoretical Computer Science, 174(4): 61–82, 2007.

    Article  Google Scholar 

  90. Richard McLaughlin, Srikanth Venkataraman, and Carlston Lim. Automated debug of speed path failures using functional tests. In Proceedings of the VLSI Test Symposium, pages 91–96, 2009.

    Google Scholar 

  91. Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Farid N Najm, and Magdy S Abadir. Maximum circuit activity estimation using pseudo-boolean satisfiability. In Proceedings of Design, Automation and Test in Europe, pages 1538–1543, 2007.

    Google Scholar 

  92. Nangate. Nangate 45nm Open Cell Library, 2011. http://www.nangate.com [accessed: 2014-05-20].

  93. Sari Onaissi, Khaled R. Heloue, and Farid N. Najm. PSTA-based branch and bound approach to the silicon speedpath isolation problem. In Proceedings of the International Conference on Computer-Aided Design, pages 217–224, 2009.

    Google Scholar 

  94. Open SystemC Initiative. TLM-2.0 Language Reference Manual, 2009. http://www.systemc.org [accessed: 2014-05-20].

  95. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, and Giovanni De Micheli. Design, synthesis, and test of networks on chips. IEEE Design & Test of Computers, 22(5):404–413, 2005.

    Google Scholar 

  96. Mihalis Psarakis, Dimitris Gizopoulos, Edgar Sánchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 27(3):4–19, 2010.

    Google Scholar 

  97. Sung-Boem Park, Ted Hong, and Subhasish Mitra. Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(10): 1545–1558, 2009.

    Article  Google Scholar 

  98. Wangqi Qiu and D. M. H. Walker. An efficient algorithm for finding the K longest testable paths through each gate in a combinational circuit. In Proceedings of the International Test Conference, pages 592–601, 2003.

    Google Scholar 

  99. Raymond Reiter. A theory of diagnosis from first principles. Artificial Intelligence, 32:57–95, 1987.

    Article  MATH  MathSciNet  Google Scholar 

  100. Jaan Raik, Vineeth Govind, and Raimund Ubar. Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Computers & Digital Techniques, 3(5):476–486, 2009.

    Article  Google Scholar 

  101. Kavita Ravi and Fabio Somenzi. Minimal assignments for bounded model checking. In Tools and Algorithms for the Construction and Analysis of Systems, volume 2988 of LNCS, pages 31–45, 2004.

    Google Scholar 

  102. Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, and Douglas L. Jones. Stochastic computation. In Proceedings of the Design Automation Conference, pages 859–864, 2010.

    Google Scholar 

  103. Matthias Sauer, Alexander Czutro, Ilia Polian, and Bernd Becker. Small-delay-fault ATPG with waveform accuracy. In Proceedings of the International Conference on Computer-Aided Design, pages 30–36, 2012.

    Google Scholar 

  104. André Sülflow and Rolf Drechsler. Automatic fault localization for programmable logic controllers. In Formal Methods for Automation and Safety in Railway and Automotive Systems, pages 247–256, 2010.

    Google Scholar 

  105. André Sülflow, Goerschwin Fey, Cécile Braunstein, Ulrich Kühne, and Rolf Drechsler. Increasing the accuracy of SAT-based debugging. In Proceedings of Design, Automation and Test in Europe, pages 1326–1332, 2009.

    Google Scholar 

  106. André Sülflow, Goerschwin Fey, Roderick Bloem, and Rolf Drechsler. Using unsatisfiable cores to debug multiple design errors. In Great Lakes Symposium VLSI, pages 77–82, 2008.

    Google Scholar 

  107. André Sülflow, Goerschwin Fey, and Rolf Drechsler. Using QBF to increase accuracy of SAT-based debugging. In Proceedings of the IEEE International Symposium on Circuits and Systems, pages 641–644, 2010.

    Google Scholar 

  108. Doochul Shin and Sandeep K. Gupta. Approximate logic synthesis for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 957–960, 2010.

    Google Scholar 

  109. Doochul Shin and Sandeep K. Gupta. A new circuit simplification method for error tolerant applications. In Proceedings of Design, Automation and Test in Europe, pages 1566–1571, 2011.

    Google Scholar 

  110. Saeed Shamshiri, Amirali Ghofrani, and Kwang-Ting Cheng. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference, pages 1–10, 2011.

    Google Scholar 

  111. Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun Nakano, Abhishek Tiwari, and Josep Torrellas. VARIUS: A model of process variation and resulting timing errors for microarchitects. IEEE Transactions Semiconductor Manufacturing, 21(1): 3–13, 2008.

    Article  Google Scholar 

  112. Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas. EVAL: Utilizing processors with variation-induced timing errors. In International Symposium on Microarchitecture, pages 423–434, 2008.

    Google Scholar 

  113. André Sülflow, Ulrich Kuhne, Goerschwin Fey, Daniel Grosse, and Rolf Drechsler. WoLFram – a word level framework for formal verification. In IEEE/IFIP International Symposium on Rapid System Prototyping, pages 11–17, 2009.

    Google Scholar 

  114. Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, and Davide Bertozzi. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of Design, Automation and Test in Europe, pages 661–666, 2011.

    Google Scholar 

  115. Sean Safarpour and Andreas Veneris. Abstraction and refinement techniques in automated design debugging. In Proceedings of Design, Automation and Test in Europe, pages 1182–1187, 2007.

    Google Scholar 

  116. Alexander Smith, Andreas Veneris, Moayad Fahim Ali, and Anastasios Viglas. Fault diagnosis and logic debugging using Boolean satisfiability. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(10):1606–1621, 2005.

    Google Scholar 

  117. Sean Safarpour, Andreas G Veneris, and Rolf Drechsler. Improved SAT-based reachability analysis with observability don’t cares. Journal of Satisfiability, Boolean Modeling and Computation, 5:1–25, 2008.

    Google Scholar 

  118. Synopsys Inc. Design Vision - Synopsys Inc., 2014. http://www.synopsys.com [accessed: 2014-05-20].

  119. Desta Tadesse, R. Iris Bahar, and Joel Grodstein. Test vector generation for post-silicon delay testing using SAT-based decision problems. Journal of Electronic Testing: Theory and Applications, 27(2):123–136, 2011.

    Google Scholar 

  120. James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, and Tanay Karnik. Resilient circuits - enabling energy-efficient performance and reliability. In Proceedings of the International Conference on Computer-Aided Design, pages 71–73, 2009.

    Google Scholar 

  121. Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, and Ulf Schlichtmann. Non-intrusive trace & debug NoC architecture with accurate timestamping for GALS SoCs. In International Conference on Hardware/Software Codesign and System Synthesis, pages 181–186, 2012.

    Google Scholar 

  122. Yanjing Li Ted Hong, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, and Subhasish Mitra. QED: Quick error detection tests for effective post-silicon validation. In Proceedings of the International Test Conference, pages 1–10, 2010.

    Google Scholar 

  123. Grigori S Tseitin. On the complexity of derivation in the propositional calculus. Zapiski nauchnykh seminarov LOMI, 8:234–259, 1968.

    Google Scholar 

  124. Shan Tang and Qiang Xu. A multi-core debug platform for NoC-based systems. In Proceedings of Design, Automation and Test in Europe, pages 870–875, 2007.

    Google Scholar 

  125. Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, and Anand Raghunathan. MACACO: Modeling and analysis of circuits for approximate computing. In Proceedings of the International Conference on Computer-Aided Design, pages 667–673, 2011.

    Google Scholar 

  126. Miroslav N Velev. Comparison of schemes for encoding unobservability in translation to SAT. In Proceedings of the ASP Design Automation Conference, pages 1056–1059, 2005.

    Google Scholar 

  127. SystemC Version. 2.0 user’s guide. Open SystemC Initiative, 2002.

    Google Scholar 

  128. Bart Vermeulen and Kees Goossens. A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs. In International Symposium on VLSI Design, Automation and Test, pages 183–186, 2009.

    Google Scholar 

  129. Andreas Veneris and Ibrahim N Hajj. Design error diagnosis and correction via test vector simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1803–1816, 1999.

    Google Scholar 

  130. Baart Vermeulen, Tom Waayers, and Sjaak Bakker. IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips. In Proceedings of the International Test Conference, pages 55–63, 2002.

    Google Scholar 

  131. Bart Vermeulen, Tom Waayers, and Sandeep Kumar Goel. Core-based scan architecture for silicon debug. In Proceedings of the International Test Conference, pages 638–647, 2002.

    Google Scholar 

  132. Lu Wan and Deming Chen. Dynatune: Circuit-level optimization for timing speculation considering dynamic path behavior. In Proceedings of the International Conference on Computer-Aided Design, pages 172–179, 2009.

    Google Scholar 

  133. Chi-Neng Wen, Shu-Hsuan Chou, Chien-Chih Chen, and Tien-Fu Chen. NUDA: A non-uniform debugging architecture and nonintrusive race detection for many-core systems. IEEE Transactions Computers, 61(2):199–212, 2012.

    Article  MathSciNet  Google Scholar 

  134. John A Waicukauski, Eric Lindbloom, Barry K Rosen, and Vijay S Iyengar. Transition fault simulation. IEEE Design & Test of Computers, 4(2):32–38, 1987.

    Google Scholar 

  135. Lin Xie and Azadeh Davoodi. Representative path selection for post-silicon timing prediction under variability. In Proceedings of the Design Automation Conference, pages 386–391, 2010.

    Google Scholar 

  136. Lin Xie and Azadeh Davoodi. Bound-based statistically-critical path extraction under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(1):59–71, 2011.

    Article  Google Scholar 

  137. Lin Xie, Azadeh Davoodi, and Kewal K. Saluja. Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. In Proceedings of the Design Automation Conference, pages 274–279, 2010.

    Google Scholar 

  138. Yu-Shen Yang, Nicola Nicolici, and Andreas G. Veneris. Automated data analysis solutions to silicon debug. In Proceedings of Design, Automation and Test in Europe, pages 982–987, 2009.

    Google Scholar 

  139. Hyunbean Yi, Sungju Park, and Sandip Kundu. On-chip support for NoC-based SoC debugging. IEEE Transactions on Circuits and Systems, 57-I(7):1608–1617, 2010.

    MathSciNet  Google Scholar 

  140. Joon-Sung Yang and Nur A. Touba. Expanding trace buffer observation window for in-system silicon debug through selective capture. In Proceedings of the VLSI Test Symposium, pages 345–351, 2008.

    Google Scholar 

  141. Joon-Sung Yang and Nur A Touba. Improved trace buffer observation via selective data capture using 2-d compaction for post-silicon debug. Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 21(2):320–328, 2013.

    Google Scholar 

  142. Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, and Ziyad Hanna. An efficient diagnostic test pattern generation framework using boolean satisfiability. In Proceedings of the ASP Design Automation Conference, pages 288–294, 2007.

    Google Scholar 

  143. Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, and Ken Amstutz. Scan based speed-path debug for a microprocessor. In European Test Symposium, pages 207–212, 2010.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Computer Science, University of Bremen, Bremen, Germany

    Mehdi Dehbashi

  2. Institute of Space Systems, German Aerospace Center, Bremen, Germany

    Görschwin Fey

Authors
  1. Mehdi Dehbashi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Görschwin Fey
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Dehbashi, M., Fey, G. (2015). Automated Debugging for Logic Bugs. In: Debug Automation from Pre-Silicon to Post-Silicon. Springer, Cham. https://doi.org/10.1007/978-3-319-09309-3_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-09309-3_3

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-09308-6

  • Online ISBN: 978-3-319-09309-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation