Abstract
There is ever increasing need for the use of computer memory and processing elements in computations. Multiple and complex instructions processing require to be carried out almost concurrently and in parallel that exhibit interleaves and inherent dependencies. Loop architectures such as unrolling loop architecture do not allow for branch/conditional instructions processing (or execution). Two-Way Loop (TWL) technique exploits instruction-level parallelism (ILP) using TWL algorithm to transform basic block loops to parallel ILP architecture to allow parallel instructions processes and executions. This paper presents TWL for concurrent executions of straight forward and branch/conditional instructions. Further evaluation of TWL algorithm is carried out in this paper.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Hennessy, J., Patterson, D.A.: Computer Architecture, 4th edn., pp. 2–104. Morgan Kaufmann Publishers Elsevier, San Francisco (2007)
Smith, J.E., Weiss, J.: PowerPC 601 and Alpha 21064: A tale of two RISCs. IEEE Journal of Computer 27(6), 46–58 (1994)
Jack, W.D., Sanjay, J.: Improving Instruction-Level Parallelism by Loop Unrolling and Dynamic Memory Disambiguation. An M.Sc. Thesis of Department of Computer Science, Thornton Hall, University of Virginia, Charlottesville, USA, pp. 1–8 (1995)
Flynn, M.J.: Computer Architecture: Pipelined and Parallel Processor Design, 1st edn., pp. 34–55. Jones and Bartlett Publishers, Inc., USA (1995) ISBN: 0867202041
Pozzi, L.: Compilation Techniques for Exploiting Instruction Level Parallelism, A Survey. Department of Electrical and Information, University of Milan, Milan. Italy Technical Report 20133, pp. 1–3 (2010)
Bacon, D.F., Graham, S.L., Sharp, O.J.: Complier Transformations for High Performance Computing. Journal of ACM Computing Surveys, 345–420 (1994)
Rau, B.R., Fisher, J.A.: Instruction-Level Parallel Processing: History Overview and Perspective. The Journal of Supercomputing 7(7), 9–50 (1993)
Pepijn, W.: Simdization Transformation Strategies - Polyhedral Transformations and Cost Estimation. An M.Sc Thesis, Department of Computer/Electrical Engineering, Delft University of Technology, Delft, Netherlands, pp. 1–77 (2012)
Vijay, S.P., Sarita, A.: Code Transformations to Improve Memory Parallelism. In: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 147–155. IEEE Computer Society, Haifa (1999)
Cantrell, C.D.: Computer System Performance Measurement. In: Unpublished Note Prepared for Lecture CE/EE 4304, Erik Jonsson School of Engineering and Computer Science, pp. 1–71. The University of Texas, Dallas (2012), http://www.utdallas.edu/~cantrell/ee4304/perf.pdf
Marcos, R.D.A., David, R.K.: Runtime Predictability of Loops. In: Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization, I.C., Ed., Austin, Texas, USA, pp. 91–98 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this paper
Cite this paper
Misra, S., Alfa, A.A., Olamide Adewale, S., Akogbe, M.A., Olaniyi, M.O. (2014). A Two-Way Loop Algorithm for Exploiting Instruction-Level Parallelism in Memory System. In: Murgante, B., et al. Computational Science and Its Applications – ICCSA 2014. ICCSA 2014. Lecture Notes in Computer Science, vol 8583. Springer, Cham. https://doi.org/10.1007/978-3-319-09156-3_19
Download citation
DOI: https://doi.org/10.1007/978-3-319-09156-3_19
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-09155-6
Online ISBN: 978-3-319-09156-3
eBook Packages: Computer ScienceComputer Science (R0)