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Hot-Carrier Degradation in Decananometer CMOS Nodes: From an Energy-Driven to a Unified Current Degradation Modeling by a Multiple-Carrier Degradation Process

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Hot Carrier Degradation in Semiconductor Devices

Abstract

As the operating temperature increases, the tradeoff between performance and reliability becomes tricky as the classical hot-carrier (HC) picture has to be modified into the energy-driven formalism, taking into account the scattering mechanisms and thermal effects in ultrashort channel, which lead to current-driven damage in nanometer-scaled MOSFETs. This chapter focuses on the new requirements for advanced modeling of HC phenomena as a function of the scaled digital CMOS nodes. In the first part we recall the classical HC behavior in both N- and P-channel MOSFETs described by the lucky electron model (LEM) in thick (T ox ≥ 7 nm) to medium-range gate-oxide thickness T ox (3.2 nm ≤ T ox ≤ 5 nm), where charge detrapping is involved. Then we present the specificity of decananometer MOSFETs (T ox < 3.2 nm) using a unified energy-driven formalism between high carrier energy to high carrier density, as now cold-carrier (CC) damage results in a multiple-particle (MP) degradation process thermally activated under multivibration excitation of the passivated dangling bonds at the interface. Next, we finally develop a complete modeling for NMOS and PMOS devices that is transferred from DC accelerating damage to AC aging involved in logic cells using an Age(t s) function, for any pulse configurations, which are readily checked between experiments on digital cells at high temperature and the modeling. HC issues and temperature intricacy with bias temperature instability (BTI) are presented through some examples. Finally, we improve the CC modeling by defining a mixed-mode (MM) damage mechanism that lies between single-particle (SP) with high carrier energy processes and MP processes dominated by carrier density, including the progressive change from electron–electron scattering (EES) to multiple-interaction scheme until MP damage. This offers a complete comparison between 28-nm low-power (SiON) silicon bulk CMOS nodes and high-K metal gate (HfSiON) submitted to MP degradation process, with the interplay of thermal effects. It opens new perspectives for an accurate HC to CC reliability determination in actual and future nanoscale CMOS nodes.

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Acknowledgments

This work has been possible thanks to the support of STMicroelectronics Crolles and particularly the help of E. Vincent, whose skills on various reliability fields have enabled us to stay involved and go further. A. Bravaix wants to give special thanks to the fruitful work of all his present and former PhD students he has supervised, and for the pleasure he has had in helping them on the road of circuit reliability, sharing their enthusiasm to improve methodologies, theoretical backgrounds, modeling, and experimental techniques, with youthful eyes that will see further than we will.

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Bravaix, A., Huard, V., Cacho, F., Federspiel, X., Roy, D. (2015). Hot-Carrier Degradation in Decananometer CMOS Nodes: From an Energy-Driven to a Unified Current Degradation Modeling by a Multiple-Carrier Degradation Process. In: Grasser, T. (eds) Hot Carrier Degradation in Semiconductor Devices. Springer, Cham. https://doi.org/10.1007/978-3-319-08994-2_3

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