Abstract
Ultra-thin body and buried oxide (UTBB) fully depleted (FD) silicon-on-insulator (SOI) MOSFETs are widely recognized as a promising candidate for 20 nm technology node and beyond, due to outstanding electrostatic control of short channel effects (SCE). Introduction of a highly-doped layer underneath thin buried oxide (BOX), so called ground-plane (GP), targets suppression of detrimental parasitic substrate coupling and opens multi-threshold voltage (V Th ) and dynamic-V Th opportunities within the same process as well as the use of back-gate control schemes [1, 2]. Electrostatics, scalability and variability issues in UTBB MOSFETs as well as their perspectives for low power digital applications are widely discussed in the literature [1–5]. At the same time assessment of UTBB FD SOI for analog and RF applications received less attention. This chapter will discuss Figures of Merit (FoM) of UTBB MOSFETs of interest for further analog/RF applications summarizing our original research over the last years [6–15]. Device analog/RF performance is assessed through the key parameters such as the transconductance, g m , the output conductance, g d , the intrinsic gain, A v and the cut-off frequencies, f T and f max. Particular attention is paid to (1) a wide-frequency band assessment, the only approach that allows fair performance prediction for analog/RF applications; (2) the effect of parasitic elements, whose impact on the device performance increases enormously in deeply downscaled devices, in which they can even dominate device performance. Whenever possible, we will compare FoM achievable in UTBB FD SOI devices with those reported for other advanced devices.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Fenouillet-Beranger, C., et al.: Efficient multi-VT FD SOI technology with UTBOX for low power circuit design. In: Proceedings of the IEEE Symposium on VLSI Technology, pp. 65–66 (2010)
Andrieu, F., et al.: Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond. In: Proceedings of the IEEE Symposium on VLSI technology, pp. 57–58 (2010)
Fenouillet-Beranger, C., et al.: Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FD SOI devices for 32 nm node and below. Solid-State Electron. 54(9), 849–854 (2010)
Monfray, S., et al.: Thin-film devices for low power applications. Solid-State Electron. 54(2), 90–96 (2010)
Burignat, S., et al.: Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel. Solid-State Electron. 54(2), 213–219 (2010)
Kilchytska, V., et al.: Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit. Solid State Electron. 70, 50–58 (2012)
Makovejev, S., et al.: Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs. Solid-State Electron. 71, 93–100 (2012)
Md Arshad, M.K., et al.: UTBB SOI MOSFETs analog figures of merit: effects of ground plane and asymmetric double-gate regime. Solid State Electron. (2013). doi:10.1016/j.sse.2013.02.051
Md Arshad, M.K., et al.: RF Behavior of undoped channel ultra-thin body with ultrathin BOX MOSFETs. In: Proceedings of the Silicon Monolitic Integrated Circuits in RF Systems (SiRF), pp. 105–108 (2012)
Makovejev, S., et al.: Comparison of small-signal output conductance frequency dependence in UTBB SOI MOSFETs with and without ground plane. In: Proceedings of the IEEE SOI Conference (2011)
Makovejev, S., et al.: On extraction of self-heating features in UTBB SOI MOSFETs. In: Proceeding of the 13th International Conference on Ultimate integration on silicon, pp. 109–112 (2012)
Kilchytska, V., Andrieu, F., Flandre, D.: On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime. In: Proceedings of the Solid State Device Research Conference (ESSDERC), pp. 246–249 (2012)
Bol, D., Kilchytska, V., De Vos, J., Andrieu, F., Flandre, D.: Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications. In: Proceedings of the IEEE SOI Conference (2012)
Kilchytska, V., Bol, D., De Vos, J., Andrieu, F., Flandre, D.: Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications. Solid-State Electron. 84, 28–37 (2013)
Md Arshad, M.K., et al.: Effect of parasitic elements on UTBB FD SOI MOSFET RF figures of merit. Solid-State Electron. 97, 38–44 (2014)
Flandre, D., Ferreira, L.F., Jespers, P.G.A., Colinge, J.-P.: Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits. Solid-State Electron. 39(4), 455–460 (1996)
Kilchytska, V., et al.: Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans. Electron Devices 50(3), 577–588 (2003)
Raskin, J.-P., Gillon, R., Chen, J., Vanhoenacker-Janvier, D., Colinge, J.-P.: Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling. IEEE Trans. Electron Devices 45(5), 1017–1025 (1998)
Parvais, B., et al.: The device architecture dilemma for CMOS technologies: opportunities and challenges of Finfet over planar mosfet. In: Proceedings of the International Symposium on VLSI Technology, Systems and Applications, pp. 80–81 (2009)
Rudenko, T., et al.: Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides. Solid-State Electron. 54(2), 164–170 (2010)
Tenbroek, B.M., Lee, M.S.L., Redman-White, W., Bunyan, R.J.T., Uren, M.J.: Self-heating effects in SOI MOSFET’s and their measurement by small signal conductance techniques. IEEE Trans. Electron Devices 43(12), 2240–2248 (1996)
Jin, W., Liu, W., Fung, S.K.H., Chan, P.C.H., Hu, C.: Self-heating characterization for SOI MOSFET based on AC output conductance. IEEE Trans. Electron Devices 48(4), 730–736 (2001)
Kilchytska, V., Levacq, D., Lederer, D., Raskin, J.-P., Flandre, D.: Floating effective backgate effect on the small-signal output conductance of SOI MOSFETs. IEEE Electron Device Lett. 24(6), 414–416 (2003)
Kilchytska, V., et al.: Substrate effect on the output conductance frequency response of SOI MOSFETs. In: Hall, S., Nazarov, A.N., Lysenko, V.S. (eds.) Nanoscaled Semiconductor-on-Insulator Structures and Devices, pp. 221–238. Springer, Dordrecht (2007)
O’Neill, A.G., et al.: Reduced self-heating by strained silicon substrate engineering. Appl. Surf. Sci. 254(19), 6182–6185 (2008)
Fiegna, C., Yang, Y., Sangiorgi, E., O’Neill, A.G.: Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation. IEEE Trans. Electron Devices 55(1), 233–244 (2008)
Braccioli, M., Curatola, G., Yang, Y., Sangiorgi, E., Fiegna, C.: Simulation of self-heating effects in different SOI MOS architectures. Solid-State Electron. 53(4), 445–451 (2009)
Kilchytska, V., et al.: Frequency variation of the small-signal output conductance of decananometer MOSFETs due to substrate cross. IEEE Electron Device Lett. 28(5), 419–421 (2007)
Kilchytska, V., Flandre, D., Raskin, J.-P.: Silicon-on-nothing MOSFETs: an efficient solution for parasitic substrate coupling suppression in SOI devices. Appl. Surf. Sci. 254(19), 6168–6173 (2008)
Khakifirooz, A., Cheng, K., Kulkarni, P.: Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications. In: Proceedings of the International Symposium on VLSI Technology, System and Applications, pp. 110–111 (2010)
Khakifirooz, A., et al.: Scalability of extremely thin SOI (ETSOI) MOSFETs to sub-20-nm gate length. IEEE Electron Device Lett. 33(2), 149–151 (2012)
Ko, C., Kuan, T., Zhang, K.: A novel CVD-SiBCN low-k spacer technology for high-speed applications. In: Proceedings of the International Symposium on VLSI Technology (2008)
Niebojewski, H., et al.: Extra-low parasitic gate-to-contacts capacitance architecture for sub-14 nm transistor nodes. In: Proceedings of the EuroSOI Conference (2013)
Ieong, M., et al.: Transistor scaling with novel materials. Mater. Today 9, 26–31 (2006)
Larson, J.M., Snyder, J.P.: Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans. Electron Devices 53(5), 1048–1058 (2006)
Connelly, D., Clifton, P.: Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018. In: Proceedings of the IEEE Electron Devices Meeting (IEDM), pp. 8–11 (2005)
Ohguro, T., Higashi, Y., Okano, K., Inaba, S., Toyoshima, Y.: The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET. In: Proceedings of the International Symposium on VLSI Technology, pp. 149–150 (2012)
Lim, T.C., Armstrong, G.A.: The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance. Solid-State Electron. 50(5), 774–783 (2006)
Acknowledgments
The work has been partly funded by the FNRS (Belgium), by the FP7 NoE ‘‘EuroSOI+’’ and by Catrene “Reaching 22” projects. The authors would like to thank Olivier Faynot, Thierry Poiroux and François Andrieu from CEA-Leti, MINATEC, Grenoble, France for the provided devices and valuable discussions as well as Pascal Simon from WELCOME characterization platform of Université catholique de Louvain, Louvain-la-Neuve, Belgium for his assistance with high-frequency measurements setup.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2014 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Kilchytska, V., Makovejev, S., Md Arshad, M.K., Raskin, JP., Flandre, D. (2014). Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications. In: Nazarov, A., Balestra, F., Kilchytska, V., Flandre, D. (eds) Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting. Engineering Materials. Springer, Cham. https://doi.org/10.1007/978-3-319-08804-4_2
Download citation
DOI: https://doi.org/10.1007/978-3-319-08804-4_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-08803-7
Online ISBN: 978-3-319-08804-4
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)