Abstract
Among different types of time-domain analog-to-digital-converters (ADCs), voltage-controlled-oscillator (VCO) based ADCs have gained prominence. Like other time-based ADCs, VCO based ADCs are amenable to CMOS technology scaling. They provide inherent anti-alias filtering to the input signal and achieve very high resolution by first order noise shaping the quantization error. Despite these advantages, traditional VCO based ADCs have found limited application due to poor linearity. Recently, several new techniques have been developed to improve the overall performance of such ADCs. This chapter briefly discusses such recent advances towards improving the performance of VCO based ADCs. A deterministic background calibration method to improve the linearity of VCO based ADCs is discussed in more detail.
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References
M. Hovin, A. Olsen, T. Lande, and C. Toumazou, “Delta-sigma modulators using frequency-modulated intermediate values,” IEEE J. Solid-State Circuits, vol. 32, no. 1, pp. 13–22, Jan. 1997.
M. Straayer and M. Perrott, “A 12-Bit, 10-MHz bandwidth, continuous-time ΣΔ ADC with a 5-Bit, 950-MS/s VCO-based quantizer,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 805–814, Apr. 2008.
U. Wismar, D. Wisland, and P. Andreani, “A 0.2 V 0.44 μW 20 kHz analog to digital ΣΔ modulator with 57 fJ/conversion FoM,” in Proc. ESSIRC, Sep. 2006, pp. 187–190.
M. Straayer, “Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Mass. Inst. Technol., Cambridge, MA, 2008.
G. Taylor and I. Galton, “A mostly-digital variable-rate continuous-time delta-sigma modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2634–2646, Dec. 2010.
J. Kim, T. Jang, Y. Yoon, and S. Cho, “Analysis and design of voltage-controlled oscillator based analog-to-digital converter,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 57, no. 1, pp. 18–30, Jan. 2010.
M. Park and M. Perrott, “A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time ΔΣ ADC with VCO-based integrator and quantizer implemented in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3344–3358, Dec. 2009.
K. Reddy, S. Rao, R. Inti, B. Young, A. Elzhasly, M. Talegaonkar, and P. Hanumolu, “A 16-mw 78-db sndr 10-mhz bw ct ΔΣ adc using residue-cancelling vco-based quantizer,” IEEE J. Solid-State Circuits, vol. 47.
A. Gupta, K. Nagaraj, and T. Viswanathan, “A two-stage ADC architecture with VCO-based second stage,” Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 58, no. 11, pp. 734–738, 2011.
S. Z. Asl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, “A 77 dB SNDR, 4 MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer,” in Custom Integrated Circuits Conference (CICC), 2011 IEEE, Sept. 2011, pp. 1–4.
G. Taylor and I. Galton, “A reconfigurable mostly-digital delta-sigma ADC with a worst-case FOM of 160 dB,” IEEE J. Solid-State Circuits, vol. 48, no. 4, pp. 983–995, Apr. 2013.
J. Daniels, W. Dehaene, M. Steyaert, and A. Wiesbauer, “A 0.02 mm2 65 nm CMOS 30 MHz BW all-digital differential VCO-based ADC with 64 dB SNDR,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2010, pp. 155–156.
S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, and P. Hanumolu, “A 71 dB SFDR open loop VCO-based ADC using 2-level PWM modulation,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2011, pp. 270–271.
S. Rao, K. Reddy, B. Young, and P. K. Hanumolu, “A 4.1 mW, 12-bit ENOB, 5 MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90 nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, 2013, pp. C68–C69.
S. Rao, K. Reddy, B. Young, and P. K. Hanumolu, "A deterministic digital background calibration technique for VCO-based ADCs,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 950–960, Apr. 2014.
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Rao, S., Hanumolu, P.K. (2015). A Deterministic Background Calibration Technique for Voltage Controlled Oscillator Based ADC. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_16
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DOI: https://doi.org/10.1007/978-3-319-07938-7_16
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