Skip to main content

Time-Domain Techniques for mm-Wave Frequency Generation

  • Chapter
  • First Online:
  • 2633 Accesses

Abstract

The demand for higher integration level and lower production cost has driven mm-wave electronics, which have traditionally been implemented in III-V technologies for better RF performance, to be also implemented in CMOS. This motivates the digitization of the mm-wave systems for improved RF performance. This paper focuses on a digitally intensive architecture and time-domain circuit and calibration techniques for mm-wave frequency synthesizer. A 60-GHz all-digital phase-locked loop (ADPLL) transmitter prototype, implemented in 65-nm CMOS, achieves excellent phase noise (−75 dBc/Hz at 10 kHz offset), fast locking (3 μs), low reference spurs (−74 dBc), and linear frequency modulation up to 1 GHz in range.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Z. Luo, A. Steegen, M. Eller, R. Mann, et al., “High performance and low power transistors integrated in 65 nm bulk CMOS technology,” IEEE Int. Electron Devices Meeting Dig. Tech. Papers, pp. 661–664, 2004.

    Google Scholar 

  2. A. Tomkins, R.A. Aroca, T. Yamamoto, S.T. Nicolson, Y. Doi, and S.P. Voinigescu, “A zero-IF 60 GHz 65 nm CMOS transceiver with direct BPSK modulation demonstrating up to 6 Gb/s data rates over a 2 m wireless link,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2085–2099, Aug. 2009.

    Google Scholar 

  3. K. Okada, N. Li, K. Matsushita, K. Bunsen, R. Murakami, A. Musa, T. Sato, H. Asada, N. Takayama, S. Ito, W. Chaivipas, R. Minami, T. Yamaguchi, Y. Takeuchi, H. Yamagishi, M. Noda, and A. Matsuzawa, “A 60-GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE802.15.3c,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2988–3004, Dec. 2011.

    Google Scholar 

  4. S. Emami, R.F. Wiser, E. Ali, M.G. Forbes, M.Q. Gordon, X. Guan, S. Lo, P.T. McElwee, J. Parker, J.R. Tani, J.M. Gilbert, and C.H. Doan, “A 60 GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 164–165, Feb. 2011.

    Google Scholar 

  5. R.B. Staszewski, and P.T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS. WILEY-Interscience, 2006.

    Google Scholar 

  6. F.M. Gardner, “Charge-pump phase-locked loops,” IEEE Trans. on Communications, vol. COMM-28, pp. 1849–1858, Nov. 1980.

    Google Scholar 

  7. R.B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J.L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I.Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O.E. Eliezer, E. de-Obaldia, and P.T. Balsara, “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, iss. 12, pp. 2278–2291, Dec. 2004.

    Google Scholar 

  8. R.B. Staszewski, J. Wallberg, S. Rezeq, C.-M. Hung, O. Eliezer, S. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-digital PLL and transmitter for mobile phones,” IEEE J. Solid-State Circuits, vol. 40, iss. 12, pp. 2469–2482, Dec. 2005.

    Google Scholar 

  9. L. Vercesi, L. Fanori, F. De Bernardinis, A. Liscidini, and R. Castello, “A dither-less all digital PLL for cellular transmitters,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1908–1920, Aug. 2012.

    Google Scholar 

  10. R.B. Staszewski, and P.T. Balsara, “Phase-domain all-digital phase-locked loop,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 52, no. 3, pp. 159–163, Mar. 2005.

    Google Scholar 

  11. K. Pourvoyeur, R. Feger, S. Schuster, A. Stelzer, and L. Maurer, “Ramp sequence analysis to resolve multi target scenarios for a 77-GHz FMCW radar sensor,” Proc. Int. Conf. on Information Fusion, pp. 1–7, June 2008.

    Google Scholar 

  12. W. Wu, J.R. Long, and R.B. Staszewski, “A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars,” Proc. IEEE Radio Frequency Integration Technolgy Symp., pp. 32–35, Dec. 2009.

    Google Scholar 

  13. G.M. Brooker, “Understanding millimeter wave FMCW radars,” Proc. Int. Conf. on Sensing Tech., pp. 152–157, Nov. 2005.

    Google Scholar 

  14. W. Wu, X. Bai, R.B. Staszewski, and J.R. Long, “A 56.4-63.4 GHz spurious free all-digital fractional-N PLL in 65 nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech Papers, pp. 352–353, Feb. 2013.

    Google Scholar 

  15. W. Wu, X. Bai, R.B. Staszewski, and J.R. Long, “A mm-wave FMCW radar transmitter based on a multirate ADPLL,” Proc. IEEE Radio Frequency Integrated Circuits Symp., pp. 107–110, June 2013.

    Google Scholar 

  16. M.E. Heidari, M. Lee, and A.A. Abidi, “All-digital outphasing modulator for a software-defined transmitter,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1260–1271, Apr. 2009.

    Google Scholar 

  17. R.B. Staszewski, D. Leipold, and P.T. Balsara, “A first multigigahertz digitally controlled oscillator for wireless applications,” Proc. IEEE Radio Frequency Integration Circuit Symp., vol. 51, no. 11, pp. 2154–2164, Nov. 2003.

    Google Scholar 

  18. J.R. Long, Y. Zhao, W. Wu, M. Spirito, L. Vera, and E. Gordon, “Passive circuit technologies for mm-wave wireless systems on silicon,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 59, no. 8, pp. 1680–1693, Aug. 2012.

    Google Scholar 

  19. W. Wu, J.R. Long, and R.B. Staszewski, “High-resolution millimeter-wave digitally-controlled oscillators with reconfigurable passive resonators,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2785–2794, Nov. 2013.

    Google Scholar 

  20. T.S.D. Cheung, J.R. Long, K. Vaed, R. Volant, A. Chinthakindi, C.M. Schnabel, J. Florkey, Z.X. He, and K. Stein, “Differentially-shielded monolithic inductors,” Proc. IEEE Custom Integrated Circuits Conf., pp. 95–98, Sept. 2003.

    Google Scholar 

  21. T. LaRocca, S.-W. Tam, D. Huang, Q. Gu, E. Socher, W. Hant, and F. Chang, “Millimeter-wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs,” IEEE Int. Microwave Symp. Dig., pp. 181–184, June 2008.

    Google Scholar 

  22. H. Sjöland, “Improved switched tuning of differential CMOS VCOs,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 5, pp. 352–355, May 2002.

    Google Scholar 

  23. M. Lee, M.E. Heidari, and A.A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse–fine time-to-digital converter with subpicosecond resolution,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808–2816, Oct. 2009.

    Google Scholar 

  24. R.B. Staszewski, G. Shriki, and P.T. Balsara, “All-digital PLL with ultra fast acquisition,” Proc. of IEEE Asian Solid-State Circuits Conf., sec. 11-7, pp. 289–292, Nov. 2005, Taipei, Taiwan.

    Google Scholar 

  25. R.B. Staszewski, J. Wallberg, G. Feygin, M. Entezari, and D. Leipold, “LMS-based calibration of an RF digitally controlled oscillator for mobile phones,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 225–229, Mar. 2006.

    Google Scholar 

  26. G. Marzin, S. Levantino, C. Samori, and A.L. Lacaita, “A 20 Mb/s phase modulator based on a 3.6 GHz digital PLL with −36 dB EVM at 5 mW power,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 2974–2988, Dec. 2012.

    Google Scholar 

  27. O. Eliezer, R.B. Staszewski, J. Mehta, F. Jabbar, and I. Bashir, “Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator,” Proc. IEEE Dallas Circuits and Systems Workshop, pp. 1–4, Oct. 2010.

    Google Scholar 

  28. R.B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P.T. Balsara, “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 220–224, Mar. 2006.

    Google Scholar 

  29. K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, “A 57-to-66 GHz quadrature PLL in 45 nm digital CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 494–495, Feb. 2009.

    Google Scholar 

  30. A. Musa, R. Murakami, T. Sato, W. Chaivipas, K. Okada, and A. Matsuzawa, “A low phase noise quadrature injection locked frequency synthesizer for mm-wave applications,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2635–2649, Nov. 2011.

    Google Scholar 

  31. X. Yi, C.C. Boon, H. Liu, J.F. Lin, J.C. Ong, and W.M. Lim, “A 57.9-to-68.3 GHz 24.6 mW frequency synthesizer with in-phase injection-coupled QVCO in 65 nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 354–355, Feb. 2013.

    Google Scholar 

  32. T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, and I. Seto, “A 77 GHz 90 nm CMOS transceiver for FMCW radar applications,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 928–937, Apr. 2010.

    Google Scholar 

  33. Y.-A. Li, M.-H. Hung, S.-J. Huang, and J. Lee, “A fully integrated 77 GHz FMCW radar system in 65 nm CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 216–217, Feb. 2010.

    Google Scholar 

  34. H. Sakurai, Y. Kobayashi, T. Mitomo, O. Watanabe, and S. Otaka, “A 1.5 GHz-modulation-range 10 ms-modulation-period 180 kHzrms-frequency-error 26 MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 292–293, Feb. 2011.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Wanghua Wu .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Wu, W., Staszewski, R.B., Long, J.R. (2015). Time-Domain Techniques for mm-Wave Frequency Generation. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_15

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-07938-7_15

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-07937-0

  • Online ISBN: 978-3-319-07938-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics