Abstract
3D integration is a promising and attractive solution for interconnect bottleneck problem, transistor scaling physical limitations, and impractical small-scale lithography. 3D integration extends Moore’s law in the third dimension, offering heterogeneous integration, higher density, lower power consumption, and faster performance. However, in order to fabricate 3D integrated circuits (ICs), new capabilities are needed: process technology, physical modeling, physical design tools, 3D architectures, design methods, and tools. The goal of this chapter is to cover the manufacturability of through silicon via (TSV)-based 3D-ICs, i.e., process technology and fabrication capability.
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H.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C.S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, S.L. Wright, 3D silicon integration. Electronic components and technology conference, 2008
Y. Xie, Processor architecture design using 3D integration technology. 23rd international conference on VLSI design, 2010
E.J. Marinissen, Y. Zorian, Testing 3D chips containing through-silicon vias. International test conference, 2009
T.M. Bauer, S.L. Shinde, J.E. Massad, D.L. Hetherington, Front end of line integration of high density, electrically isolated, metallized through silicon vias. Electronic components and technology conference, 2009
D.Y. Chen, W.C. Chiou, M.F. Chen, T.D. Wang, K.M. Ching, Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking. IEEE, 2009
A. Klumpp, P. Ramm, R. Wieland, 3D-integration of silicon devices: a key technology for sophisticated products. Date, 2010
C. Laviron, B. Dunne, V. Lapras, P. Galbiati, D. Henry, F. Toia, S. Moreau, R. Anciant, C.B. Manquat, N. Sillon, Via first approach optimisation for through silicon via applications. Electronic components and technology conference, 2009
R. Weerasekera, M. Grange, D. Pamunuwa, On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits. Date, 2010
M. Koyanagi, T. Fukushima, T. Tanaka, Three-dimensional integration technology and integrated systems. IEEE, 2009
http://www.suss.com/markets/3d-integration/tsv-manufacturing.html. Accessed 2012.
http://www.austriamicrosystems.com/. Accessed 2012.
Y. Civale, D.S. Tezcan, H.G.G. Philipsen, P. Jaenen, R. Agarwal, F. Duval, P. Soussan, Y. Travaly, E. Beyne, Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. IEEE, 2009
M.J. Wolf, P. Ramm, A. Klumpp, H. Reichl, Technologies for 3D wafer level heterogeneous. DTIP, 2008
S.Q. Gu, U. Ray, Y. Li, A. Chandrasekaran, B. Henderson, M. Nowak, 3D TSV integration technology challenges for high volume production from fabless supply chain aspect. IEEE, 2010
C. Huyghebaert, J.V. Olmen, Y. Civale, A. Phommahaxay, A. Jourdain, S. Sood, S. Farrens, P. Soussan, Cu to Cu interconnect using 3D-TSV and Wafer to Wafer thermo compression bonding. IEEE, 2010
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Salah, K., Ismail, Y., El-Rouby, A. (2015). TSV Fabrication. In: Arbitrary Modeling of TSVs for 3D Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07611-9_9
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DOI: https://doi.org/10.1007/978-3-319-07611-9_9
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