Abstract
Interconnect dimensions and complementary metal–oxide–semiconductor (CMOS) transistor feature sizes approach their physical limits. Therefore, scaling will no longer be the sole contributor to performance improvement. In addition to trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a high-performance heterogeneous system is a major trend. This chapter briefly surveys key technology level trends, classified as “More Moore” such as: new architectures (silicon on insulator, SOI; FinFET; Twin-Well) and new materials (High-K, metal gate, strained Si), “More than Moore” such as: new interconnect schemes (three-dimensional, 3D; network on chip, NoC; optical; wireless), and “Beyond CMOS” such as: new devices (molecular computer, biological computer, quantum computer).
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Salah, K., Ismail, Y., El-Rouby, A. (2015). Introduction: Work Around Moore’s Law. In: Arbitrary Modeling of TSVs for 3D Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07611-9_1
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DOI: https://doi.org/10.1007/978-3-319-07611-9_1
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