Abstract
This chapter presents new strategies for the analysis and model order reduction of systems of ever-growing size and complexity by exploiting the hierarchical structure of analog electronical circuits. Thereby, the entire circuit is considered as a system of interconnected subcircuits. Given a prescribed error-bound for the reduction process, a newly developed algorithm tries to achieve a maximal reduction degree for the overall system by choosing the reduction degrees of the subcircuits in a convenient way. The individual subsystem reductions with respect to their prescribed error-bound are then performed using different reduction techniques. Combining the reduced subsystems a reduced model of the overall system results. Finally, the usability of the new techniques is demonstrated on two circuit examples typically used in industrial applications.
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Notes
- 1.
For doing it best, we first have to determine the voltage and current sources of the circuit that can act as inputs. Thus, the corresponding independent value of each port has to be considered as output. If you connect a voltage source at a port p this would be the current through port p, and vice versa.
For simplicity, we use here voltage sources as inputs and the currents as outputs. Besides of that, it turns out that residual based solvers simulate analog circuits containing transistors faster and more accurate if the voltages are given at the circuit’s ports instead of the currents.
- 2.
Assume we are dealing with systems of DAEs. If PDEs are involved, apply a semidiscretization w.r.t. the spatial coordinates.
- 3.
See Remarks 4.2.2.
- 4.
Minimal with respect to the corresponding error \(E(y,y_{\,\,\widetilde{T}_{ i}^{(\,j)}})\).
- 5.
For a vector X = (x 1, …, x n ), deleting the entry x i in X means, that a vector \(\tilde{X} = (x_{1},\ldots,x_{i-1},x_{i+1},\ldots,x_{n})\) of dimension n − 1 results.
- 6.
The computations are performed on a Dual Quad Xeon E5420 with 2.5 MHz and 16 GB RAM.
- 7.
A term ranking is a trade-off between accuracy and efficiency in computation time that estimates the influence of a term in a system of equations on its solution. Here, however, we use full simulations instead of low-accuracy estimates. For more details see [20].
- 8.
Due to the structure preserving reduction method, the resulting reduced model contains equations connecting the models of the subcircuits, that can be avoided, like: Voltage of node 24 of subcircuit LS is equal to the voltage of node 24 of subcircuit PP.
Unifying the corresponding variables (i.e. V$24$LS and V$24$PP) yields a decrease of the number of equations.
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Schmidt, O., Hauser, M., Lang, P. (2017). Coupling of Numeric/Symbolic Reduction Methods for Generating Parametrized Models of Nanoelectronic Systems. In: Benner, P. (eds) System Reduction for Nanoscale IC Design. Mathematics in Industry, vol 20. Springer, Cham. https://doi.org/10.1007/978-3-319-07236-4_4
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