Abstract
This chapter introduces checkers—SystemVerilog units containing verification code. Checkers may combine assertions, covergroups, and modeling code in order to create verification IP. Checkers are more flexible than modules and interfaces since they allow a wider variety of types of their arguments, and since they may be instantiated in procedural code. This chapter covers checker declaration and instantiation, and explains their scheduling semantics.
Contradictions do not exist. Whenever you think you are facing a contradiction, check your premises. You will find that one of them is wrong.— Ayn Rand
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- 1.
Except arguments with local qualifier, see Sect. 16.2.
- 2.
Not to be confused with passing events to modules. In case of modules it is possible to pass a variable of the type event. Here we pass the entire event expression, such as posedge clk by substitution.
- 3.
More exactly, its usage is deprecated in checkers.
- 4.
The LRM is not clear about placing immediate assertions in checkers. In any case it should be safe to place immediate assertions in action blocks of concurrent assertions.
- 5.
In the SystemVerilog 2009 standard only general purpose always procedures have been allowed in checkers. But the SystemVerilog 2012 standard introduced specialized always procedures in checkers and the general purpose always procedure has been deprecated.
References
IEEE Std. 1800–2012, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language (2012)
Accellera. Accellera Standard Open Verification Library (OVL) V2.8 (2013)
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Checkers. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_9
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DOI: https://doi.org/10.1007/978-3-319-07139-8_9
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