Abstract
In SystemVerilog, modules, programs, interfaces, checkers, functions, and tasks provide means for reuse, and for abstracting and hiding details. SystemVerilog assertions provide such means too. This is achieved using parameterized let, sequence, and property declarations. Their argument lists as well as instantiation semantics are quite different from the other reuse features. In addition, certain kinds of actual arguments can be inferred from the instantiation context. Similar to sequences and properties, let declarations allow to abstract expressions, making code more readable and reusable. let can be used anywhere, not only in assertions. One of their intended uses is for defining reusable parameterizable expressions for immediate and deferred assertions.
The beginning of wisdom is to call things by their right names.
Chinese proverb
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Notes
- 1.
The compiler may issue a warning for the second macro definition, saying that the symbol has been redefined.
- 2.
The SystemVerilog LRM provides many examples illustrating the use of let in various scoping contexts, with and without typed arguments and type casting, as well as the use of sampled value functions in let definitions.
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Let, Sequence and Property Declarations; Inference. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_8
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DOI: https://doi.org/10.1007/978-3-319-07139-8_8
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-07139-8
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