Abstract
The enhancements to the IEEE SystemVerilog language in the 2009 and 2012 standards and, in particular, to the SystemVerilog Assertions (SVA) allow us to create much more useful and versatile checker libraries. In this chapter, we first identify the weaknesses of the current checker libraries by examining an example from the OVL library. We then provide a classification of checkers, and show how various forms of effective checker libraries can be created using the new constructs. We use the term checker and checker library in a broad sense to denote a verification unit and library, possibly assertion based. We refer to the SystemVerilog checker construct using checker.
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Notes
- 1.
Port enable is not used in the OVL checker, so it is not included in this description.
- 2.
If a system function existed that allowed to distinguish Boolean expressions from temporal sequences and properties, a conditional generate could be used to construct different forms of properties depending on the actual argument.
References
Accellera. Universal Verification Methodology (UVM) 1.1 (2011)
Accellera. Accellera Standard Open Verification Library (OVL) V2.8 (2013)
J. Bergeron, E. Cerny, A. Hunter, A. Nightingale, Verification Methodology Manual for SystemVerilog (Springer, New York, 2006)
E. Cerny, D. Korchemny, L. Piper, E. Selingman, S. Dudani, Verification case studies: evolution from sva 2005 to sva 2009, in Proceedings of Design Verification Conference, DVCon, (Accellera System Initiative, 2009)
M. Glasser. Open Verification Methodology Cookbook (Springer, New York, 2009)
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© 2015 Springer International Publishing Switzerland
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Cerny, E., Dudani, S., Havlicek, J., Korchemny, D. (2015). Checker Libraries. In: SVA: The Power of Assertions in SystemVerilog. Springer, Cham. https://doi.org/10.1007/978-3-319-07139-8_24
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DOI: https://doi.org/10.1007/978-3-319-07139-8_24
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